@@ -64,6 +64,7 @@ typedef struct
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uint8_t stage ;
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void * buffer ;
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tuh_msc_complete_cb_t complete_cb ;
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+ uintptr_t complete_arg ;
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msc_cbw_t cbw ;
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msc_csw_t csw ;
@@ -126,7 +127,7 @@ static inline void cbw_init(msc_cbw_t *cbw, uint8_t lun)
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cbw -> lun = lun ;
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}
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- bool tuh_msc_scsi_command (uint8_t dev_addr , msc_cbw_t const * cbw , void * data , tuh_msc_complete_cb_t complete_cb )
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+ bool tuh_msc_scsi_command (uint8_t dev_addr , msc_cbw_t const * cbw , void * data , tuh_msc_complete_cb_t complete_cb , uintptr_t arg )
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{
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msch_interface_t * p_msc = get_itf (dev_addr );
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TU_VERIFY (p_msc -> configured );
@@ -137,13 +138,14 @@ bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tu
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p_msc -> stage = MSC_STAGE_CMD ;
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p_msc -> buffer = data ;
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p_msc -> complete_cb = complete_cb ;
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+ p_msc -> complete_arg = arg ;
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TU_ASSERT (usbh_edpt_xfer (dev_addr , p_msc -> ep_out , (uint8_t * ) & p_msc -> cbw , sizeof (msc_cbw_t )));
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return true;
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}
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- bool tuh_msc_read_capacity (uint8_t dev_addr , uint8_t lun , scsi_read_capacity10_resp_t * response , tuh_msc_complete_cb_t complete_cb )
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+ bool tuh_msc_read_capacity (uint8_t dev_addr , uint8_t lun , scsi_read_capacity10_resp_t * response , tuh_msc_complete_cb_t complete_cb , uintptr_t arg )
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{
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msch_interface_t * p_msc = get_itf (dev_addr );
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TU_VERIFY (p_msc -> configured );
@@ -156,10 +158,10 @@ bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_r
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cbw .cmd_len = sizeof (scsi_read_capacity10_t );
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cbw .command [0 ] = SCSI_CMD_READ_CAPACITY_10 ;
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- return tuh_msc_scsi_command (dev_addr , & cbw , response , complete_cb );
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+ return tuh_msc_scsi_command (dev_addr , & cbw , response , complete_cb , arg );
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}
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- bool tuh_msc_inquiry (uint8_t dev_addr , uint8_t lun , scsi_inquiry_resp_t * response , tuh_msc_complete_cb_t complete_cb )
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+ bool tuh_msc_inquiry (uint8_t dev_addr , uint8_t lun , scsi_inquiry_resp_t * response , tuh_msc_complete_cb_t complete_cb , uintptr_t arg )
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{
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msch_interface_t * p_msc = get_itf (dev_addr );
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TU_VERIFY (p_msc -> mounted );
@@ -178,10 +180,10 @@ bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* respons
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};
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memcpy (cbw .command , & cmd_inquiry , cbw .cmd_len );
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- return tuh_msc_scsi_command (dev_addr , & cbw , response , complete_cb );
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+ return tuh_msc_scsi_command (dev_addr , & cbw , response , complete_cb , arg );
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}
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- bool tuh_msc_test_unit_ready (uint8_t dev_addr , uint8_t lun , tuh_msc_complete_cb_t complete_cb )
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+ bool tuh_msc_test_unit_ready (uint8_t dev_addr , uint8_t lun , tuh_msc_complete_cb_t complete_cb , uintptr_t arg )
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{
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msch_interface_t * p_msc = get_itf (dev_addr );
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TU_VERIFY (p_msc -> configured );
@@ -195,10 +197,10 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_
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cbw .command [0 ] = SCSI_CMD_TEST_UNIT_READY ;
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cbw .command [1 ] = lun ; // according to wiki TODO need verification
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- return tuh_msc_scsi_command (dev_addr , & cbw , NULL , complete_cb );
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+ return tuh_msc_scsi_command (dev_addr , & cbw , NULL , complete_cb , arg );
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}
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- bool tuh_msc_request_sense (uint8_t dev_addr , uint8_t lun , void * resposne , tuh_msc_complete_cb_t complete_cb )
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+ bool tuh_msc_request_sense (uint8_t dev_addr , uint8_t lun , void * resposne , tuh_msc_complete_cb_t complete_cb , uintptr_t arg )
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{
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msc_cbw_t cbw ;
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cbw_init (& cbw , lun );
@@ -215,10 +217,10 @@ bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_ms
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memcpy (cbw .command , & cmd_request_sense , cbw .cmd_len );
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- return tuh_msc_scsi_command (dev_addr , & cbw , resposne , complete_cb );
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+ return tuh_msc_scsi_command (dev_addr , & cbw , resposne , complete_cb , arg );
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}
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- bool tuh_msc_read10 (uint8_t dev_addr , uint8_t lun , void * buffer , uint32_t lba , uint16_t block_count , tuh_msc_complete_cb_t complete_cb )
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+ bool tuh_msc_read10 (uint8_t dev_addr , uint8_t lun , void * buffer , uint32_t lba , uint16_t block_count , tuh_msc_complete_cb_t complete_cb , uintptr_t arg )
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{
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msch_interface_t * p_msc = get_itf (dev_addr );
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TU_VERIFY (p_msc -> mounted );
@@ -239,10 +241,10 @@ bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba,
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memcpy (cbw .command , & cmd_read10 , cbw .cmd_len );
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- return tuh_msc_scsi_command (dev_addr , & cbw , buffer , complete_cb );
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+ return tuh_msc_scsi_command (dev_addr , & cbw , buffer , complete_cb , arg );
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}
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- bool tuh_msc_write10 (uint8_t dev_addr , uint8_t lun , void const * buffer , uint32_t lba , uint16_t block_count , tuh_msc_complete_cb_t complete_cb )
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+ bool tuh_msc_write10 (uint8_t dev_addr , uint8_t lun , void const * buffer , uint32_t lba , uint16_t block_count , tuh_msc_complete_cb_t complete_cb , uintptr_t arg )
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{
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msch_interface_t * p_msc = get_itf (dev_addr );
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TU_VERIFY (p_msc -> mounted );
@@ -263,7 +265,7 @@ bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_
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memcpy (cbw .command , & cmd_write10 , cbw .cmd_len );
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- return tuh_msc_scsi_command (dev_addr , & cbw , (void * )(uintptr_t ) buffer , complete_cb );
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+ return tuh_msc_scsi_command (dev_addr , & cbw , (void * )(uintptr_t ) buffer , complete_cb , arg );
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}
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#if 0
@@ -344,7 +346,17 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
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// SCSI op is complete
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p_msc -> stage = MSC_STAGE_IDLE ;
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- if (p_msc -> complete_cb ) p_msc -> complete_cb (dev_addr , cbw , csw );
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+ if (p_msc -> complete_cb )
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+ {
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+ tuh_msc_complete_data_t const cb_data =
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+ {
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+ .cbw = cbw ,
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+ .csw = csw ,
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+ .scsi_data = p_msc -> buffer ,
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+ .user_arg = p_msc -> complete_arg
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+ };
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+ p_msc -> complete_cb (dev_addr , & cb_data );
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+ }
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break ;
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// unknown state
@@ -359,9 +371,9 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
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//--------------------------------------------------------------------+
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static void config_get_maxlun_complete (tuh_xfer_t * xfer );
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- static bool config_test_unit_ready_complete (uint8_t dev_addr , msc_cbw_t const * cbw , msc_csw_t const * csw );
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- static bool config_request_sense_complete (uint8_t dev_addr , msc_cbw_t const * cbw , msc_csw_t const * csw );
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- static bool config_read_capacity_complete (uint8_t dev_addr , msc_cbw_t const * cbw , msc_csw_t const * csw );
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+ static bool config_test_unit_ready_complete (uint8_t dev_addr , tuh_msc_complete_data_t const * cb_data );
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+ static bool config_request_sense_complete (uint8_t dev_addr , tuh_msc_complete_data_t const * cb_data );
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+ static bool config_read_capacity_complete (uint8_t dev_addr , tuh_msc_complete_data_t const * cb_data );
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bool msch_open (uint8_t rhport , uint8_t dev_addr , tusb_desc_interface_t const * desc_itf , uint16_t max_len )
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{
@@ -446,37 +458,46 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer)
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// TODO multiple LUN support
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TU_LOG2 ("SCSI Test Unit Ready\r\n" );
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uint8_t const lun = 0 ;
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- tuh_msc_test_unit_ready (daddr , lun , config_test_unit_ready_complete );
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+ tuh_msc_test_unit_ready (daddr , lun , config_test_unit_ready_complete , 0 );
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}
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- static bool config_test_unit_ready_complete (uint8_t dev_addr , msc_cbw_t const * cbw , msc_csw_t const * csw )
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+ static bool config_test_unit_ready_complete (uint8_t dev_addr , tuh_msc_complete_data_t const * cb_data )
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{
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+ msc_cbw_t const * cbw = cb_data -> cbw ;
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+ msc_csw_t const * csw = cb_data -> csw ;
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+
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if (csw -> status == 0 )
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{
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// Unit is ready, read its capacity
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TU_LOG2 ("SCSI Read Capacity\r\n" );
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- tuh_msc_read_capacity (dev_addr , cbw -> lun , (scsi_read_capacity10_resp_t * ) ((void * ) _msch_buffer ), config_read_capacity_complete );
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+ tuh_msc_read_capacity (dev_addr , cbw -> lun , (scsi_read_capacity10_resp_t * ) ((void * ) _msch_buffer ), config_read_capacity_complete , 0 );
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}else
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{
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// Note: During enumeration, some device fails Test Unit Ready and require a few retries
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// with Request Sense to start working !!
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// TODO limit number of retries
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TU_LOG2 ("SCSI Request Sense\r\n" );
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- TU_ASSERT (tuh_msc_request_sense (dev_addr , cbw -> lun , _msch_buffer , config_request_sense_complete ));
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+ TU_ASSERT (tuh_msc_request_sense (dev_addr , cbw -> lun , _msch_buffer , config_request_sense_complete , 0 ));
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}
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return true;
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}
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- static bool config_request_sense_complete (uint8_t dev_addr , msc_cbw_t const * cbw , msc_csw_t const * csw )
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+ static bool config_request_sense_complete (uint8_t dev_addr , tuh_msc_complete_data_t const * cb_data )
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{
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+ msc_cbw_t const * cbw = cb_data -> cbw ;
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+ msc_csw_t const * csw = cb_data -> csw ;
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+
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TU_ASSERT (csw -> status == 0 );
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- TU_ASSERT (tuh_msc_test_unit_ready (dev_addr , cbw -> lun , config_test_unit_ready_complete ));
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+ TU_ASSERT (tuh_msc_test_unit_ready (dev_addr , cbw -> lun , config_test_unit_ready_complete , 0 ));
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return true;
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}
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- static bool config_read_capacity_complete (uint8_t dev_addr , msc_cbw_t const * cbw , msc_csw_t const * csw )
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+ static bool config_read_capacity_complete (uint8_t dev_addr , tuh_msc_complete_data_t const * cb_data )
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{
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+ msc_cbw_t const * cbw = cb_data -> cbw ;
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+ msc_csw_t const * csw = cb_data -> csw ;
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+
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TU_ASSERT (csw -> status == 0 );
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msch_interface_t * p_msc = get_itf (dev_addr );
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