about L2 cache issues.

[weijizhen]

Hello!
Why did RTX2060 not call this method (m_L2cache ->fill), but did L2 cache still have data?

[JRPan]

There are two fill functions. One for allocation on fill and one for allocation on miss. Check both. Also, during cudaMemcpy the data are prefetched into L2 by default.

[weijizhen]

Part of the data is shown below. What happens when there is an L2 cache miss?
(The logic I know is to initiate a request for DRAM and then fill the data back into the L2 cache, but it seems that the data has not been cached into the L2 cache, nor has it gone through the process of m_dram_L2_queue. pop())

L2_cache_bank[0]: Access = 32, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[1]: Access = 32, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[2]: Access = 32, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[3]: Access = 4, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[4]: Access = 32, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[5]: Access = 32, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[6]: Access = 32, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[7]: Access = 4, Miss = 0, Miss_rate = 0.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[8]: Access = 32, Miss = 32, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[9]: Access = 32, Miss = 32, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[10]: Access = 32, Miss = 32, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[11]: Access = 4, Miss = 4, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_cache_bank[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L2_total_cache_accesses = 300
L2_total_cache_misses = 100
L2_total_cache_miss_rate = 0.3333

In Dram Latency Queue (total = 0):
DRAM[11]: 16 bks, busW=2 BL=16 CL=20, tRRD=10 tCCD=4, tRCD=20 tRAS=50 tRP=20 tRC=62
n_cmd=19316 n_nop=19316 n_act=0 n_pre=0 n_ref_event=0 n_req=0 n_rd=0 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0
n_activity=0 dram_eff=-nan
bk0: 0a 19316i bk1: 0a 19316i bk2: 0a 19316i bk3: 0a 19316i bk4: 0a 19316i bk5: 0a 19316i bk6: 0a 19316i bk7: 0a 19316i bk8: 0a 19316i bk9: 0a 19316i bk10: 0a 19316i bk11: 0a 19316i bk12: 0a 19316i bk13: 0a 19316i bk14: 0a 19316i bk15: 0a 19316i

[JRPan]

SM Load -> L1 miss -> L2 miss -> DRAM load -> data in L2 -> data in L1 -> data in SM

[weijizhen]

When I was debugging, I speculated that it might be returning to L1 cache or searching for data in registers, as there was no DRAM access or prefetching. So, I want to ask you to take a look.
Additionally, what methods or variables indicate that the data required by the thread has been obtained? I want to know which storage unit this thread obtained data from.
Please reply, thank you!

[JRPan]

By default all data loads should come from L1D. If for some reason L1D is bypassed then the data is loaded from L2.

[weijizhen]

Yes, I can understand your answer. Thank you very much.
Although my test data is very small, in the RTX2060 test, there was an L2 cache miss (access type is GLOBAL_ACC_W), which did not enter DRAM processing. Instead, it was directly returned to SM through: "m_L2_icnt_queue". Why is this?

[weijizhen]

In addition. When accessing (L2 cache), there will be two situations: (miss) and (hit). Why do both situations execute this (m_L2_icnt_queue ->push (mf);)? If an L2 cache miss occurs, should this be executed （m_L2_dram_queue->push(mf);）?
gpgpu-sim_distribution/src/gpgpu-sim/l2cache.cc:547

[weijizhen]

Can you help me answer the doubts mentioned above? I have been waiting for your reply!!!

[JRPan]

Please check http://gpgpu-sim.org/manual/index.php/Main_Page for the details.