Merge pull request #14 from edanuff/main

clean up Enhanced build

Author: edanuff

.gitattributes

@@ -6,7 +6,7 @@ impl/** linguist-vendored
 boards/a2n9/impl/** linguist-vendored
 boards/a2n20v1/impl/** linguist-vendored
 boards/a2n20v2/impl/** linguist-vendored
-boards/a2n20v2-SDRAM/impl/** linguist-vendored
+boards/a2n20v2_enhanced/impl/** linguist-vendored
 
 src/picosoc/libraries/ff/** linguist-vendored
 src/picosoc/libraries/pff/** linguist-vendored

README.md

@@ -97,7 +97,7 @@ For ROM 00/01 IIgs models (such as the Woz edition), the A2N20v2 must be placed
 
 [A2N20v2 Board Support Project (Schematics, Project Files)](boards/a2n20v2/)
 
-[A2N20v2 Board Support Project (Experimental SDRAM Feature Set)](boards/a2n20v2-SDRAM/)
+[A2N20v2 Board Support Project (Experimental SDRAM Feature Set)](boards/a2n20v2_enhanced/)
 
 ### Using the A2N9
 

boards/a2n20v2-SDRAM/README.md renamed to boards/a2n20v2-Enhanced/README.md

@@ -1,9 +1,10 @@
-# A2N20v2 Card (Experimental SDRAM feature set)
+# A2N20v2 Card Enhanced (Work In Progress)
 
 This is the project version that builds the FPGA bitstream for the 
 [Tang Nano 20K](https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html)
 version of the A2FPGA Apple II card.  It is intended to provide an advanced
-feature set that requires the use of the Tang Nano 20K's 8MB of SDRAM.
+feature set that includes a RiscV SoftCore that requires the use of the 
+Tang Nano 20K's 8MB of SDRAM and SD Card slot.
 
 The A2N20v2 version supports Apple II, //e, and IIgs models. The v2 card uses a 100-pin 
 "a2bridge" CPLD that captures all Apple II, //e, and IIgs signals including the
@@ -19,8 +20,12 @@ main A2N20v2 release.
 
 New features that this project provides include:
 
+- Persistent storage of configuration settings such as enabling and disabling virtual
+cards without requiring different firmware builds, making it easier to resolve compatibility
+issues with installed physical cards.
+
 - Moving Apple II Graphics VRAM to SDRAM for more efficient use of FPGA resources, enabling
-more features to be implemented in the FPGA. (IIgs graphics still use FPGA blockram
+more features to be implemented in the FPGA. (IIgs graphics still use FPGA BlockRam
 for performance)
 
 - A PicoRV32 RiscV 32-bit co-processor that provides SD-Card support for mounting
@@ -43,10 +48,10 @@ For ROM 00/01 IIgs models (such as the Woz edition), the A2N20v2 must be placed
 
 To update the bitstream on the A2N20v2, the most convenient way is to use [OpenFPGALoader](https://github.com/trabucayre/openFPGALoader)
 Mac users with [Homebrew](https://brew.sh/) can just type `brew install openfpgaloader` in the Terminal to install it
-Use OpenFPGALoader to program the Tang Nano 20K board via USB with the [a2n20v2.fs](impl/pnr/a2n20v2.fs) bistream file and run `openfpgaloader -b tangnano20k -f a2n20v2.fs`
+Use OpenFPGALoader to program the Tang Nano 20K board via USB with the [a2n20v2_enhanced.fs](impl/pnr/a2n20v2_enhanced.fs) bistream file and run `openfpgaloader -b tangnano20k -f a2n20v2_enhanced.fs`
 
 The project can also be opened and built with the Gowin IDE, either educational
-or commercial editions.  Use the `a2n20v2.gprj` file in this folder.
+or commercial editions.  Use the `a2n20v2_enhanced.gprj` file in this folder.
 
 Note: When using the Gowin IDE, do not add or remove files from the project or it will
 turn the relative file paths into absolute file paths.

boards/a2n20v2-SDRAM/a2n20v2-SDRAM.gprj renamed to boards/a2n20v2-Enhanced/a2n20v2_enhanced.gprj

@@ -56,8 +56,8 @@
         <File path="../../hdl/video/vgc.sv" type="file.verilog" enable="1"/>
         <File path="../../hdl/video/video_control_if.sv" type="file.verilog" enable="1"/>
         <File path="../../hdl/video/video.hex" type="file.other" enable="1"/>
-        <File path="hdl/a2n20v2-SDRAM.cst" type="file.cst" enable="1"/>
-        <File path="hdl/a2n20v2-SDRAM.sdc" type="file.sdc" enable="1"/>
+        <File path="hdl/a2n20v2_enhanced.cst" type="file.cst" enable="1"/>
+        <File path="hdl/a2n20v2_enhanced.sdc" type="file.sdc" enable="1"/>
         <File path="hdl/bus/apple_bus.sv" type="file.verilog" enable="1"/>
         <File path="hdl/gowin/clk_hdmi/clk_hdmi.v" type="file.verilog" enable="1"/>
         <File path="hdl/gowin/clk_logic/clk_logic.v" type="file.verilog" enable="1"/>

boards/a2n20v2-SDRAM/hdl/a2n20v2-SDRAM.cst renamed to boards/a2n20v2-Enhanced/hdl/a2n20v2_enhanced.cst

@@ -1,4 +1,4 @@
-// 2N20v2-SDRAM - Tang Nano 20K SDRAM implementation of Apple II memory
+// 2N20v2_enhanced - Tang Nano 20K SDRAM implementation of Apple II memory
 //
 // (c) 2023,2024 Ed Anuff <ed@a2fpga.com> 
 //

boards/a2n20v2-SDRAM/hdl/a2n20v2-SDRAM.sdc renamed to boards/a2n20v2-Enhanced/hdl/a2n20v2_enhanced.sdc

@@ -50,15 +50,15 @@ <h1><a name="Message">Pin Messages</a></h1>
 </tr>
 <tr>
 <td class="label">Design File</td>
-<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\impl\gwsynthesis\a2n20v2-SDRAM.vg</td>
+<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\impl\gwsynthesis\a2n20v2_enhanced.vg</td>
 </tr>
 <tr>
 <td class="label">Physical Constraints File</td>
-<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.cst</td>
+<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2_enhanced.cst</td>
 </tr>
 <tr>
 <td class="label">Timing Constraints File</td>
-<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.sdc</td>
+<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2_enhanced.sdc</td>
 </tr>
 <tr>
 <td class="label">Version</td>
@@ -78,7 +78,7 @@ <h1><a name="Message">Pin Messages</a></h1>
 </tr>
 <tr>
 <td class="label">Created Time</td>
-<td>Sun Mar 03 10:19:32 2024
+<td>Thu Aug 22 19:01:37 2024
 </td>
 </tr>
 <tr>

boards/a2n20v2-SDRAM/hdl/bus/apple_bus.sv renamed to boards/a2n20v2-Enhanced/hdl/bus/apple_bus.sv

@@ -59,15 +59,15 @@ <h1><a name="Message">Power Messages</a></h1>
 </tr>
 <tr>
 <td class="label">Design File</td>
-<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\impl\gwsynthesis\a2n20v2-SDRAM.vg</td>
+<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\impl\gwsynthesis\a2n20v2_enhanced.vg</td>
 </tr>
 <tr>
 <td class="label">Physical Constraints File</td>
-<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.cst</td>
+<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2_enhanced.cst</td>
 </tr>
 <tr>
 <td class="label">Timing Constraints File</td>
-<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.sdc</td>
+<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2_enhanced.sdc</td>
 </tr>
 <tr>
 <td class="label">Version</td>
@@ -87,7 +87,7 @@ <h1><a name="Message">Power Messages</a></h1>
 </tr>
 <tr>
 <td class="label">Created Time</td>
-<td>Sun Mar 03 10:19:32 2024
+<td>Thu Aug 22 19:01:37 2024
 </td>
 </tr>
 <tr>
@@ -100,30 +100,30 @@ <h2><a name="Power_Info">Power Information:</a></h2>
 <table class="summary_table">
 <tr>
 <td class="label">Total Power (mW)</td>
-<td>305.201</td>
+<td>305.213</td>
 </tr>
 <tr>
 <td class="label">Quiescent Power (mW)</td>
 <td>93.224</td>
 </tr>
 <tr>
 <td class="label">Dynamic Power (mW)</td>
-<td>211.977</td>
+<td>211.988</td>
 </tr>
 </table>
 <h2><a name="Thermal_Info">Thermal Information:</a></h2>
 <table class="summary_table">
 <tr>
 <td class="label">Junction Temperature</td>
-<td>34.107</td>
+<td>34.108</td>
 </tr>
 <tr>
 <td class="label">Theta JA</td>
 <td>29.840</td>
 </tr>
 <tr>
 <td class="label">Max Allowed Ambient Temperature</td>
-<td>75.893</td>
+<td>75.892</td>
 </tr>
 </table>
 <h2><a name="Configure_Info">Configure Information:</a></h2>
@@ -192,9 +192,9 @@ <h2><a name="Supply_Summary">Supply Information:</a></h2>
 <tr>
 <td>VCC</td>
 <td>1.000</td>
-<td>187.520</td>
+<td>187.531</td>
 <td>61.515</td>
-<td>249.035</td>
+<td>249.046</td>
 </tr>
 <tr>
 <td>VCCX</td>
@@ -222,9 +222,9 @@ <h2><a name="By_Block_Type">Power By Block Type:</a></h2>
 </tr>
 <tr>
 <td>Logic</td>
-<td>5.159</td>
+<td>5.170</td>
 <td>NA</td>
-<td>5.601</td>
+<td>5.596</td>
 </tr>
 <tr>
 <td>IO</td>
@@ -248,7 +248,7 @@ <h2><a name="By_Block_Type">Power By Block Type:</a></h2>
 <td>DSP</td>
 <td>1.033
 <td>NA</td>
-<td>3.973
+<td>3.980
 </tr>
 </table>
 <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
@@ -260,28 +260,28 @@ <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
 </tr>
 <tr>
 <td>top</td>
-<td>183.220</td>
-<td>183.220(182.892)</td>
+<td>183.232</td>
+<td>183.232(182.901)</td>
 <tr>
 <td>top/apple_bus/</td>
-<td>0.104</td>
-<td>0.104(0.000)</td>
+<td>0.105</td>
+<td>0.105(0.000)</td>
 <tr>
 <td>top/apple_memory/</td>
-<td>119.063</td>
-<td>119.063(119.001)</td>
+<td>119.062</td>
+<td>119.062(119.000)</td>
 <tr>
 <td>top/apple_memory/hires_aux_2000_5FFF/</td>
-<td>59.500</td>
-<td>59.500(0.000)</td>
-<tr>
-<td>top/apple_memory/hires_aux_6000_9FFF/</td>
 <td>59.501</td>
 <td>59.501(0.000)</td>
 <tr>
+<td>top/apple_memory/hires_aux_6000_9FFF/</td>
+<td>59.499</td>
+<td>59.499(0.000)</td>
+<tr>
 <td>top/apple_video/</td>
-<td>0.552</td>
-<td>0.552(0.000)</td>
+<td>0.557</td>
+<td>0.557(0.000)</td>
 <tr>
 <td>top/cdc_phi1/</td>
 <td>0.001</td>
@@ -296,24 +296,24 @@ <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
 <td>5.649(0.000)</td>
 <tr>
 <td>top/hdmi/</td>
-<td>0.499</td>
-<td>0.499(0.460)</td>
+<td>0.504</td>
+<td>0.504(0.464)</td>
 <tr>
 <td>top/hdmi/tmds_gen[0].tmds_channel/</td>
 <td>0.054</td>
 <td>0.054(0.000)</td>
 <tr>
 <td>top/hdmi/tmds_gen[1].tmds_channel/</td>
-<td>0.050</td>
-<td>0.050(0.000)</td>
+<td>0.052</td>
+<td>0.052(0.000)</td>
 <tr>
 <td>top/hdmi/tmds_gen[2].tmds_channel/</td>
-<td>0.050</td>
-<td>0.050(0.000)</td>
+<td>0.052</td>
+<td>0.052(0.000)</td>
 <tr>
 <td>top/hdmi/true_hdmi_output.packet_assembler/</td>
-<td>0.109</td>
-<td>0.109(0.000)</td>
+<td>0.110</td>
+<td>0.110(0.000)</td>
 <tr>
 <td>top/hdmi/true_hdmi_output.packet_picker/</td>
 <td>0.196</td>
@@ -324,48 +324,48 @@ <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
 <td>0.048(0.000)</td>
 <tr>
 <td>top/mockingboard/</td>
-<td>1.063</td>
-<td>1.063(1.063)</td>
+<td>1.065</td>
+<td>1.065(1.065)</td>
 <tr>
 <td>top/mockingboard/m6522_left/</td>
-<td>0.194</td>
-<td>0.194(0.000)</td>
+<td>0.195</td>
+<td>0.195(0.000)</td>
 <tr>
 <td>top/mockingboard/m6522_right/</td>
-<td>0.192</td>
-<td>0.192(0.000)</td>
+<td>0.189</td>
+<td>0.189(0.000)</td>
 <tr>
 <td>top/mockingboard/psg_left/</td>
-<td>0.336</td>
-<td>0.336(0.000)</td>
-<tr>
-<td>top/mockingboard/psg_right/</td>
 <td>0.341</td>
 <td>0.341(0.000)</td>
 <tr>
+<td>top/mockingboard/psg_right/</td>
+<td>0.340</td>
+<td>0.340(0.000)</td>
+<tr>
 <td>top/sdram_ports/</td>
-<td>0.221</td>
-<td>0.221(0.221)</td>
+<td>0.222</td>
+<td>0.222(0.222)</td>
 <tr>
 <td>top/sdram_ports/sdram_inst/</td>
-<td>0.221</td>
-<td>0.221(0.000)</td>
+<td>0.222</td>
+<td>0.222(0.000)</td>
 <tr>
 <td>top/supersprite/</td>
-<td>41.547</td>
-<td>41.547(41.468)</td>
+<td>41.543</td>
+<td>41.543(41.464)</td>
 <tr>
 <td>top/supersprite/ssp_psg/</td>
-<td>0.342</td>
-<td>0.342(0.000)</td>
+<td>0.343</td>
+<td>0.343(0.000)</td>
 <tr>
 <td>top/supersprite/vdp/</td>
-<td>41.126</td>
-<td>41.126(41.126)</td>
+<td>41.121</td>
+<td>41.121(41.121)</td>
 <tr>
 <td>top/supersprite/vdp/f18a_core/</td>
-<td>41.126</td>
-<td>41.126(41.123)</td>
+<td>41.121</td>
+<td>41.121(41.118)</td>
 <tr>
 <td>top/supersprite/vdp/f18a_core/inst_color/</td>
 <td>0.036</td>
@@ -376,16 +376,16 @@ <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
 <td>0.062(0.000)</td>
 <tr>
 <td>top/supersprite/vdp/f18a_core/inst_cpu/</td>
-<td>0.599</td>
-<td>0.599(0.000)</td>
+<td>0.600</td>
+<td>0.600(0.000)</td>
 <tr>
 <td>top/supersprite/vdp/f18a_core/inst_sprites/</td>
-<td>8.543</td>
-<td>8.543(0.000)</td>
+<td>8.544</td>
+<td>8.544(0.000)</td>
 <tr>
 <td>top/supersprite/vdp/f18a_core/inst_tiles/</td>
-<td>2.173</td>
-<td>2.173(0.314)</td>
+<td>2.168</td>
+<td>2.168(0.314)</td>
 <tr>
 <td>top/supersprite/vdp/f18a_core/inst_tiles/inst_linebuf/</td>
 <td>0.314</td>
@@ -404,8 +404,8 @@ <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
 <td>29.643(0.000)</td>
 <tr>
 <td>top/vgc/</td>
-<td>0.074</td>
-<td>0.074(0.000)</td>
+<td>0.072</td>
+<td>0.072(0.000)</td>
 </table>
 <h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
 <table class="detail_table">
@@ -415,14 +415,14 @@ <h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
 <th class="label">Total Dynamic Power(mW)</th>
 </tr>
 <tr>
-<td>clk_pixel</td>
-<td>27.000</td>
-<td>15.547</td>
-</tr>
-<tr>
 <td>clk_logic</td>
 <td>54.000</td>
-<td>162.046</td>
+<td>162.051</td>
+</tr>
+<tr>
+<td>clk_pixel</td>
+<td>27.000</td>
+<td>15.555</td>
 </tr>
 <tr>
 <td>NO CLOCK DOMAIN</td>