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rename files & folders for Enhanced firmware
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‎.gitattributes

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@@ -6,7 +6,7 @@ impl/** linguist-vendored
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boards/a2n9/impl/** linguist-vendored
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boards/a2n20v1/impl/** linguist-vendored
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boards/a2n20v2/impl/** linguist-vendored
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boards/a2n20v2-SDRAM/impl/** linguist-vendored
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boards/a2n20v2-Enhanced/impl/** linguist-vendored
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src/picosoc/libraries/ff/** linguist-vendored
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src/picosoc/libraries/pff/** linguist-vendored

‎README.md

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@@ -97,7 +97,7 @@ For ROM 00/01 IIgs models (such as the Woz edition), the A2N20v2 must be placed
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[A2N20v2 Board Support Project (Schematics, Project Files)](boards/a2n20v2/)
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[A2N20v2 Board Support Project (Experimental SDRAM Feature Set)](boards/a2n20v2-SDRAM/)
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[A2N20v2 Board Support Project (Experimental SDRAM Feature Set)](boards/a2n20v2-Enhanced/)
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### Using the A2N9
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‎boards/a2n20v2-SDRAM/README.md renamed to ‎boards/a2n20v2-Enhanced/README.md

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# A2N20v2 Card (Experimental SDRAM feature set)
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# A2N20v2 Card Enhanced (Work In Progress)
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This is the project version that builds the FPGA bitstream for the
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[Tang Nano 20K](https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html)
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version of the A2FPGA Apple II card. It is intended to provide an advanced
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feature set that requires the use of the Tang Nano 20K's 8MB of SDRAM.
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feature set that includes a RiscV SoftCore that requires the use of the
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Tang Nano 20K's 8MB of SDRAM and SD Card slot.
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The A2N20v2 version supports Apple II, //e, and IIgs models. The v2 card uses a 100-pin
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"a2bridge" CPLD that captures all Apple II, //e, and IIgs signals including the
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New features that this project provides include:
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- Persistent storage of configuration settings such as enabling and disabling virtual
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cards without requiring different firmware builds, making it easier to resolve compatibility
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issues with installed physical cards.
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- Moving Apple II Graphics VRAM to SDRAM for more efficient use of FPGA resources, enabling
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more features to be implemented in the FPGA. (IIgs graphics still use FPGA blockram
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more features to be implemented in the FPGA. (IIgs graphics still use FPGA BlockRam
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for performance)
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- A PicoRV32 RiscV 32-bit co-processor that provides SD-Card support for mounting
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To update the bitstream on the A2N20v2, the most convenient way is to use [OpenFPGALoader](https://github.com/trabucayre/openFPGALoader)
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Mac users with [Homebrew](https://brew.sh/) can just type `brew install openfpgaloader` in the Terminal to install it
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Use OpenFPGALoader to program the Tang Nano 20K board via USB with the [a2n20v2.fs](impl/pnr/a2n20v2.fs) bistream file and run `openfpgaloader -b tangnano20k -f a2n20v2.fs`
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Use OpenFPGALoader to program the Tang Nano 20K board via USB with the [a2n20v2_enhanced.fs](impl/pnr/a2n20v2_enhanced.fs) bistream file and run `openfpgaloader -b tangnano20k -f a2n20v2_enhanced.fs`
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The project can also be opened and built with the Gowin IDE, either educational
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or commercial editions. Use the `a2n20v2.gprj` file in this folder.
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or commercial editions. Use the `a2n20v2_enhanced.gprj` file in this folder.
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Note: When using the Gowin IDE, do not add or remove files from the project or it will
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turn the relative file paths into absolute file paths.

‎boards/a2n20v2-SDRAM/a2n20v2-SDRAM.gprj renamed to ‎boards/a2n20v2-Enhanced/a2n20v2_enhanced.gprj

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<File path="../../hdl/video/vgc.sv" type="file.verilog" enable="1"/>
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<File path="../../hdl/video/video_control_if.sv" type="file.verilog" enable="1"/>
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<File path="../../hdl/video/video.hex" type="file.other" enable="1"/>
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<File path="hdl/a2n20v2-SDRAM.cst" type="file.cst" enable="1"/>
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<File path="hdl/a2n20v2-SDRAM.sdc" type="file.sdc" enable="1"/>
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<File path="hdl/a2n20v2-Enhanced.cst" type="file.cst" enable="1"/>
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<File path="hdl/a2n20v2-Enhanced.sdc" type="file.sdc" enable="1"/>
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<File path="hdl/bus/apple_bus.sv" type="file.verilog" enable="1"/>
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<File path="hdl/gowin/clk_hdmi/clk_hdmi.v" type="file.verilog" enable="1"/>
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<File path="hdl/gowin/clk_logic/clk_logic.v" type="file.verilog" enable="1"/>

‎boards/a2n20v2-SDRAM/hdl/a2n20v2-SDRAM.cst renamed to ‎boards/a2n20v2-Enhanced/hdl/a2n20v2_enhanced.cst

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‎boards/a2n20v2-SDRAM/hdl/a2n20v2-SDRAM.sdc renamed to ‎boards/a2n20v2-Enhanced/hdl/a2n20v2_enhanced.sdc

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‎boards/a2n20v2-SDRAM/hdl/gowin/clk_hdmi/clk_hdmi.ipc renamed to ‎boards/a2n20v2-Enhanced/hdl/gowin/clk_hdmi/clk_hdmi.ipc

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‎boards/a2n20v2-SDRAM/hdl/gowin/clk_hdmi/clk_hdmi.v renamed to ‎boards/a2n20v2-Enhanced/hdl/gowin/clk_hdmi/clk_hdmi.v

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‎boards/a2n20v2-SDRAM/hdl/gowin/clk_hdmi/clk_hdmi_tmp.v renamed to ‎boards/a2n20v2-Enhanced/hdl/gowin/clk_hdmi/clk_hdmi_tmp.v

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‎boards/a2n20v2-SDRAM/hdl/gowin/clk_logic/clk_logic.ipc renamed to ‎boards/a2n20v2-Enhanced/hdl/gowin/clk_logic/clk_logic.ipc

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‎boards/a2n20v2-SDRAM/hdl/gowin/clk_logic/clk_logic.v renamed to ‎boards/a2n20v2-Enhanced/hdl/gowin/clk_logic/clk_logic.v

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‎boards/a2n20v2-SDRAM/hdl/gowin/clk_logic/clk_logic_tmp.v renamed to ‎boards/a2n20v2-Enhanced/hdl/gowin/clk_logic/clk_logic_tmp.v

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‎boards/a2n20v2-SDRAM/hdl/memory/apple_memory.sv renamed to ‎boards/a2n20v2-Enhanced/hdl/memory/apple_memory.sv

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// 2N20v2-SDRAM - Tang Nano 20K SDRAM implementation of Apple II memory
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// 2N20v2-Enhanced - Tang Nano 20K SDRAM implementation of Apple II memory
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//
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// (c) 2023,2024 Ed Anuff <ed@a2fpga.com>
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//

‎boards/a2n20v2-SDRAM/hdl/top.sv renamed to ‎boards/a2n20v2-Enhanced/hdl/top.sv

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‎boards/a2n20v2-SDRAM/impl/pnr/a2n20v2-SDRAM.fs renamed to ‎boards/a2n20v2-Enhanced/impl/pnr/a2n20v2_enhanced.fs

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‎boards/a2n20v2-SDRAM/impl/pnr/a2n20v2-SDRAM.pin.html renamed to ‎boards/a2n20v2-Enhanced/impl/pnr/a2n20v2_enhanced.pin.html

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</tr>
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<td class="label">Design File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\impl\gwsynthesis\a2n20v2-SDRAM.vg</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\impl\gwsynthesis\a2n20v2-Enhanced.vg</td>
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</tr>
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<td class="label">Physical Constraints File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.cst</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2-Enhanced.cst</td>
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</tr>
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<td class="label">Timing Constraints File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.sdc</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2-Enhanced.sdc</td>
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</tr>
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<tr>
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<td class="label">Version</td>

‎boards/a2n20v2-SDRAM/impl/pnr/a2n20v2-SDRAM.power.html renamed to ‎boards/a2n20v2-Enhanced/impl/pnr/a2n20v2_enhanced.power.html

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<td class="label">Design File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\impl\gwsynthesis\a2n20v2-SDRAM.vg</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\impl\gwsynthesis\a2n20v2-Enhanced.vg</td>
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<td class="label">Physical Constraints File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.cst</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2-Enhanced.cst</td>
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<td class="label">Timing Constraints File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.sdc</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2-Enhanced.sdc</td>
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<td class="label">Version</td>

‎boards/a2n20v2-SDRAM/impl/pnr/a2n20v2-SDRAM.rpt.html renamed to ‎boards/a2n20v2-Enhanced/impl/pnr/a2n20v2_enhanced.rpt.html

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<td class="label">Design File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\impl\gwsynthesis\a2n20v2-SDRAM.vg</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\impl\gwsynthesis\a2n20v2-Enhanced.vg</td>
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<td class="label">Physical Constraints File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.cst</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2-Enhanced.cst</td>
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<td class="label">Timing Constraints File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.sdc</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2-Enhanced.sdc</td>
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<td class="label">Version</td>

‎boards/a2n20v2-SDRAM/impl/pnr/a2n20v2-SDRAM.rpt.txt renamed to ‎boards/a2n20v2-Enhanced/impl/pnr/a2n20v2_enhanced.rpt.txt

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1. PnR Messages
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<Report Title>: PnR Report
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<Design File>: C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\impl\gwsynthesis\a2n20v2-SDRAM.vg
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<Physical Constraints File>: C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.cst
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<Timing Constraints File>: C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.sdc
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<Design File>: C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\impl\gwsynthesis\a2n20v2-Enhanced.vg
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<Physical Constraints File>: C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2-Enhanced.cst
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<Timing Constraints File>: C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2-Enhanced.sdc
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<PnR Version>: V1.9.9 Beta-4 Education
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<Part Number>: GW2AR-LV18QN88C8/I7
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<Device>: GW2AR-18

‎boards/a2n20v2-SDRAM/impl/pnr/a2n20v2-SDRAM.tr.html renamed to ‎boards/a2n20v2-Enhanced/impl/pnr/a2n20v2_enhanced.tr.html

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<title>Timing Analysis Report</title>
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‎boards/a2n20v2-Enhanced/impl/pnr/a2n20v2_enhanced_tr_cata.html

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<!-- messages begin-->
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<li><div class="triangle_fake"></div><a href="a2n20v2-Enhanced_tr_content.html#Route_Congestions_Report" style=" font-size: 14px;" target="mainFrame">Route Congestions Report</a></li>
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<li><div class="triangle" onclick="onClick(this)"></div><a href="a2n20v2-Enhanced_tr_content.html#Timing_Exceptions_Report" style=" font-size: 14px;" target="mainFrame">Timing Exceptions Report</a>
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<ul>
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<!--Setup_Analysis_Exceptions begin-->
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<li><div class="triangle_fake"></div><a href="a2n20v2-Enhanced_tr_content.html#Setup_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
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<li><div class="triangle_fake"></div><a href="a2n20v2-Enhanced_tr_content.html#Hold_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
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<li><div class="triangle_fake"></div><a href="a2n20v2-Enhanced_tr_content.html#Recovery_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
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<li><div class="triangle_fake" onclick="onClick(this)"></div><a href="a2n20v2-Enhanced_tr_content.html#Removal_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
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</ul>
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</div><!-- catalog -->
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</html>

‎boards/a2n20v2-SDRAM/impl/pnr/a2n20v2-SDRAM_tr_content.html renamed to ‎boards/a2n20v2-Enhanced/impl/pnr/a2n20v2_enhanced_tr_content.html

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</tr>
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<td class="label">Design File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\impl\gwsynthesis\a2n20v2-SDRAM.vg</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\impl\gwsynthesis\a2n20v2-Enhanced.vg</td>
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<td class="label">Physical Constraints File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.cst</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2-Enhanced.cst</td>
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<td class="label">Timing Constraint File</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-SDRAM\hdl\a2n20v2-SDRAM.sdc</td>
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<td>C:\Users\ed\GitHub\a2fpga_core\boards\a2n20v2-Enhanced\hdl\a2n20v2-Enhanced.sdc</td>
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<td class="label">Version</td>

‎boards/a2n20v2-SDRAM/impl/pnr/device.cfg renamed to ‎boards/a2n20v2-Enhanced/impl/pnr/device.cfg

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‎boards/a2n20v2-SDRAM/impl/project_process_config.json renamed to ‎boards/a2n20v2-Enhanced/impl/project_process_config.json

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"Number_of_Critical_Paths" : "",
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"Number_of_Start/End_Points" : "",
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"OSC_DIVIDER" : "8",
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"OUTPUT_BASE_NAME" : "a2n20v2-SDRAM",
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"OUTPUT_BASE_NAME" : "a2n20v2-Enhanced",
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"POWER_ON_RESET_MONITOR" : true,
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"PRINT_BSRAM_VALUE" : true,
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"PROGRAM_DONE_BYPASS" : false,

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