rename files & folders for Enhanced firmware

Author: edanuff

.gitattributes

@@ -6,7 +6,7 @@ impl/** linguist-vendored
 boards/a2n9/impl/** linguist-vendored
 boards/a2n20v1/impl/** linguist-vendored
 boards/a2n20v2/impl/** linguist-vendored
-boards/a2n20v2-SDRAM/impl/** linguist-vendored
+boards/a2n20v2-Enhanced/impl/** linguist-vendored
 
 src/picosoc/libraries/ff/** linguist-vendored
 src/picosoc/libraries/pff/** linguist-vendored

README.md

@@ -97,7 +97,7 @@ For ROM 00/01 IIgs models (such as the Woz edition), the A2N20v2 must be placed
 
 [A2N20v2 Board Support Project (Schematics, Project Files)](boards/a2n20v2/)
 
-[A2N20v2 Board Support Project (Experimental SDRAM Feature Set)](boards/a2n20v2-SDRAM/)
+[A2N20v2 Board Support Project (Experimental SDRAM Feature Set)](boards/a2n20v2-Enhanced/)
 
 ### Using the A2N9
 

boards/a2n20v2-SDRAM/README.md renamed to boards/a2n20v2-Enhanced/README.md

@@ -1,9 +1,10 @@
-# A2N20v2 Card (Experimental SDRAM feature set)
+# A2N20v2 Card Enhanced (Work In Progress)
 
 This is the project version that builds the FPGA bitstream for the 
 [Tang Nano 20K](https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html)
 version of the A2FPGA Apple II card.  It is intended to provide an advanced
-feature set that requires the use of the Tang Nano 20K's 8MB of SDRAM.
+feature set that includes a RiscV SoftCore that requires the use of the 
+Tang Nano 20K's 8MB of SDRAM and SD Card slot.
 
 The A2N20v2 version supports Apple II, //e, and IIgs models. The v2 card uses a 100-pin 
 "a2bridge" CPLD that captures all Apple II, //e, and IIgs signals including the
@@ -19,8 +20,12 @@ main A2N20v2 release.
 
 New features that this project provides include:
 
+- Persistent storage of configuration settings such as enabling and disabling virtual
+cards without requiring different firmware builds, making it easier to resolve compatibility
+issues with installed physical cards.
+
 - Moving Apple II Graphics VRAM to SDRAM for more efficient use of FPGA resources, enabling
-more features to be implemented in the FPGA. (IIgs graphics still use FPGA blockram
+more features to be implemented in the FPGA. (IIgs graphics still use FPGA BlockRam
 for performance)
 
 - A PicoRV32 RiscV 32-bit co-processor that provides SD-Card support for mounting
@@ -43,10 +48,10 @@ For ROM 00/01 IIgs models (such as the Woz edition), the A2N20v2 must be placed
 
 To update the bitstream on the A2N20v2, the most convenient way is to use [OpenFPGALoader](https://github.com/trabucayre/openFPGALoader)
 Mac users with [Homebrew](https://brew.sh/) can just type `brew install openfpgaloader` in the Terminal to install it
-Use OpenFPGALoader to program the Tang Nano 20K board via USB with the [a2n20v2.fs](impl/pnr/a2n20v2.fs) bistream file and run `openfpgaloader -b tangnano20k -f a2n20v2.fs`
+Use OpenFPGALoader to program the Tang Nano 20K board via USB with the [a2n20v2_enhanced.fs](impl/pnr/a2n20v2_enhanced.fs) bistream file and run `openfpgaloader -b tangnano20k -f a2n20v2_enhanced.fs`
 
 The project can also be opened and built with the Gowin IDE, either educational
-or commercial editions.  Use the `a2n20v2.gprj` file in this folder.
+or commercial editions.  Use the `a2n20v2_enhanced.gprj` file in this folder.
 
 Note: When using the Gowin IDE, do not add or remove files from the project or it will
 turn the relative file paths into absolute file paths.

boards/a2n20v2-SDRAM/a2n20v2-SDRAM.gprj renamed to boards/a2n20v2-Enhanced/a2n20v2_enhanced.gprj

@@ -56,8 +56,8 @@
         <File path="../../hdl/video/vgc.sv" type="file.verilog" enable="1"/>
         <File path="../../hdl/video/video_control_if.sv" type="file.verilog" enable="1"/>
         <File path="../../hdl/video/video.hex" type="file.other" enable="1"/>
-        <File path="hdl/a2n20v2-SDRAM.cst" type="file.cst" enable="1"/>
-        <File path="hdl/a2n20v2-SDRAM.sdc" type="file.sdc" enable="1"/>
+        <File path="hdl/a2n20v2-Enhanced.cst" type="file.cst" enable="1"/>
+        <File path="hdl/a2n20v2-Enhanced.sdc" type="file.sdc" enable="1"/>
         <File path="hdl/bus/apple_bus.sv" type="file.verilog" enable="1"/>
         <File path="hdl/gowin/clk_hdmi/clk_hdmi.v" type="file.verilog" enable="1"/>
         <File path="hdl/gowin/clk_logic/clk_logic.v" type="file.verilog" enable="1"/>