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edanuffedanuff
committed
fix BUS_DATA_OUT_ENABLE switch to properly disengage card from data bus
1 parent 4cb08a4 commit 3d3d2a7

25 files changed

+4110
-3113
lines changed

‎boards/a2n20v1/hdl/bus/apple_bus.sv

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,8 @@
2525
//
2626

2727
module apple_bus #(
28+
parameter bit IRQ_OUT_ENABLE = 1,
29+
parameter bit BUS_DATA_OUT_ENABLE = 1,
2830
parameter int CLOCK_SPEED_HZ = 50_000_000,
2931
parameter int APPLE_HZ = 14_318_181,
3032
parameter int CPU_HZ = APPLE_HZ / 14, // 1_022_727
@@ -71,7 +73,7 @@ module apple_bus #(
7173
if (!a2bus_if.device_reset_n) begin
7274
control_out_r <= 8'hFF;
7375
end else begin
74-
control_out_r[2] <= irq_n_i;
76+
control_out_r[2] <= irq_n_i || !IRQ_OUT_ENABLE;
7577
end
7678
end
7779

@@ -263,7 +265,7 @@ module apple_bus #(
263265

264266
end
265267

266-
assign a2_bridge_bus_d_oe_o = data_out_en_i;
268+
assign a2_bridge_bus_d_oe_o = data_out_en_i & BUS_DATA_OUT_ENABLE;
267269

268270
assign a2bus_if.data_in_strobe = data_in_strobe_r;
269271

‎boards/a2n20v1/hdl/top.sv

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,9 @@ module top #(
190190
);
191191

192192
apple_bus #(
193-
.CLOCK_SPEED_HZ(CLOCK_SPEED_HZ)
193+
.CLOCK_SPEED_HZ(CLOCK_SPEED_HZ),
194+
.BUS_DATA_OUT_ENABLE(BUS_DATA_OUT_ENABLE),
195+
.IRQ_OUT_ENABLE(IRQ_OUT_ENABLE)
194196
) apple_bus (
195197
.a2bus_if(a2bus_if),
196198

@@ -450,7 +452,7 @@ module top #(
450452

451453
// Interrupts
452454

453-
assign irq_n_w = (mb_irq_n && vdp_irq_n && ssc_irq_n) || !IRQ_OUT_ENABLE;
455+
assign irq_n_w = mb_irq_n && vdp_irq_n && ssc_irq_n;
454456

455457
// Audio
456458

‎boards/a2n20v1/impl/pnr/a2n20v1.fs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
//SecureMode: OFF
1818
//JTAGAsRegularIO: OFF
1919
//MultiBootSPIAddr: 0x00000000
20-
//Created Time: Thu Apr 25 19:11:24 2024
20+
//Created Time: Wed Jun 19 15:01:19 2024
2121
1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
2222
1111111111111111
2323
1010010111000011

‎boards/a2n20v1/impl/pnr/a2n20v1.pin.html

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ <h1><a name="Message">Pin Messages</a></h1>
7878
</tr>
7979
<tr>
8080
<td class="label">Created Time</td>
81-
<td>Thu Apr 25 19:11:25 2024
81+
<td>Wed Jun 19 15:01:20 2024
8282
</td>
8383
</tr>
8484
<tr>

‎boards/a2n20v1/impl/pnr/a2n20v1.power.html

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ <h1><a name="Message">Power Messages</a></h1>
8787
</tr>
8888
<tr>
8989
<td class="label">Created Time</td>
90-
<td>Thu Apr 25 19:11:25 2024
90+
<td>Wed Jun 19 15:01:20 2024
9191
</td>
9292
</tr>
9393
<tr>
@@ -452,16 +452,16 @@ <h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
452452
<td>18.785</td>
453453
</tr>
454454
<tr>
455-
<td>clk_logic</td>
456-
<td>54.000</td>
457-
<td>252.155</td>
458-
</tr>
459-
<tr>
460455
<td>NO CLOCK DOMAIN</td>
461456
<td>0.000</td>
462457
<td>0.000</td>
463458
</tr>
464459
<tr>
460+
<td>clk_logic</td>
461+
<td>54.000</td>
462+
<td>252.155</td>
463+
</tr>
464+
<tr>
465465
<td>clk_hdmi</td>
466466
<td>135.000</td>
467467
<td>0.009</td>

‎boards/a2n20v1/impl/pnr/a2n20v1.rpt.html

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ <h1><a name="Message">PnR Messages</a></h1>
8383
</tr>
8484
<tr>
8585
<td class="label">Created Time</td>
86-
<td>Thu Apr 25 19:11:26 2024
86+
<td>Wed Jun 19 15:01:20 2024
8787
</td>
8888
</tr>
8989
<tr>
@@ -97,24 +97,24 @@ <h1><a name="PnR_Details">PnR Details</a></h1>
9797
<tr>
9898
<td class="label">Place & Route Process</td>
9999
<td>Running placement:
100-
Placement Phase 0: CPU time = 0h 0m 0.856s, Elapsed time = 0h 0m 0.856s
101-
Placement Phase 1: CPU time = 0h 0m 0.209s, Elapsed time = 0h 0m 0.209s
100+
Placement Phase 0: CPU time = 0h 0m 0.847s, Elapsed time = 0h 0m 0.846s
101+
Placement Phase 1: CPU time = 0h 0m 0.2s, Elapsed time = 0h 0m 0.2s
102102
Placement Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
103103
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
104104
Total Placement: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
105105
Running routing:
106106
Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
107-
Routing Phase 1: CPU time = 0h 0m 0.252s, Elapsed time = 0h 0m 0.252s
107+
Routing Phase 1: CPU time = 0h 0m 0.244s, Elapsed time = 0h 0m 0.244s
108108
Routing Phase 2: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
109109
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
110110
Total Routing: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
111111
Generate output files:
112-
CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
112+
CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
113113
</td>
114114
</tr>
115115
<tr>
116116
<td class="label">Total Time and Memory Usage</td>
117-
<td>CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 391MB</td>
117+
<td>CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s, Peak memory usage = 346MB</td>
118118
</tr>
119119
</table>
120120
<br/>

‎boards/a2n20v1/impl/pnr/a2n20v1.rpt.txt

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -12,27 +12,27 @@
1212
<Part Number>: GW2AR-LV18QN88C8/I7
1313
<Device>: GW2AR-18
1414
<Device Version>: C
15-
<Created Time>:Thu Apr 25 19:11:26 2024
15+
<Created Time>:Wed Jun 19 15:01:20 2024
1616

1717

1818
2. PnR Details
1919

2020
Running placement:
21-
Placement Phase 0: CPU time = 0h 0m 0.856s, Elapsed time = 0h 0m 0.856s
22-
Placement Phase 1: CPU time = 0h 0m 0.209s, Elapsed time = 0h 0m 0.209s
21+
Placement Phase 0: CPU time = 0h 0m 0.847s, Elapsed time = 0h 0m 0.846s
22+
Placement Phase 1: CPU time = 0h 0m 0.2s, Elapsed time = 0h 0m 0.2s
2323
Placement Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
2424
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
2525
Total Placement: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
2626
Running routing:
2727
Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
28-
Routing Phase 1: CPU time = 0h 0m 0.252s, Elapsed time = 0h 0m 0.252s
28+
Routing Phase 1: CPU time = 0h 0m 0.244s, Elapsed time = 0h 0m 0.244s
2929
Routing Phase 2: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
3030
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
3131
Total Routing: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
3232
Generate output files:
33-
CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
33+
CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
3434

35-
Total Time and Memory Usage: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 391MB
35+
Total Time and Memory Usage: CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s, Peak memory usage = 346MB
3636

3737

3838
3. Resource Usage Summary

‎boards/a2n20v1/impl/pnr/a2n20v1_tr_content.html

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ <h1><a name="Message">Timing Messages</a></h1>
5555
</tr>
5656
<tr>
5757
<td class="label">Created Time</td>
58-
<td>Thu Apr 25 19:11:26 2024
58+
<td>Wed Jun 19 15:01:20 2024
5959
</td>
6060
</tr>
6161
<tr>

‎boards/a2n20v2-SDRAM/hdl/bus/apple_bus.sv

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@
99
//
1010

1111
module apple_bus #(
12+
parameter bit IRQ_OUT_ENABLE = 1,
13+
parameter bit BUS_DATA_OUT_ENABLE = 1,
1214
parameter int CLOCK_SPEED_HZ = 50_000_000,
1315
parameter int APPLE_HZ = 14_318_181,
1416
parameter int CPU_HZ = APPLE_HZ / 14, // 1_022_727
@@ -55,7 +57,7 @@ module apple_bus #(
5557
if (!a2bus_if.device_reset_n) begin
5658
control_out_r <= 8'hFF;
5759
end else begin
58-
control_out_r[2] <= irq_n_i;
60+
control_out_r[2] <= irq_n_i || !IRQ_OUT_ENABLE;
5961
end
6062
end
6163

@@ -257,7 +259,7 @@ module apple_bus #(
257259

258260
end
259261

260-
assign a2_bridge_bus_d_oe_n_o = !data_out_en_i;
262+
assign a2_bridge_bus_d_oe_n_o = ~(data_out_en_i & BUS_DATA_OUT_ENABLE);
261263

262264
assign a2bus_if.data_in_strobe = data_in_strobe_r;
263265

‎boards/a2n20v2-SDRAM/hdl/top.sv

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -261,7 +261,9 @@ module top #(
261261
);
262262

263263
apple_bus #(
264-
.CLOCK_SPEED_HZ(CLOCK_SPEED_HZ)
264+
.CLOCK_SPEED_HZ(CLOCK_SPEED_HZ),
265+
.BUS_DATA_OUT_ENABLE(BUS_DATA_OUT_ENABLE),
266+
.IRQ_OUT_ENABLE(IRQ_OUT_ENABLE)
265267
) apple_bus (
266268
.a2bus_if(a2bus_if),
267269

@@ -621,7 +623,7 @@ module top #(
621623

622624
// Interrupts
623625

624-
assign irq_n_w = (mb_irq_n && vdp_irq_n && ssc_irq_n) || !IRQ_OUT_ENABLE;
626+
assign irq_n_w = mb_irq_n && vdp_irq_n && ssc_irq_n;
625627

626628
// HDMI
627629

‎boards/a2n20v2/hdl/bus/apple_bus.sv

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,8 @@
2525
//
2626

2727
module apple_bus #(
28+
parameter bit IRQ_OUT_ENABLE = 1,
29+
parameter bit BUS_DATA_OUT_ENABLE = 1,
2830
parameter int CLOCK_SPEED_HZ = 50_000_000,
2931
parameter int APPLE_HZ = 14_318_181,
3032
parameter int CPU_HZ = APPLE_HZ / 14, // 1_022_727
@@ -71,7 +73,7 @@ module apple_bus #(
7173
if (!a2bus_if.device_reset_n) begin
7274
control_out_r <= 8'hFF;
7375
end else begin
74-
control_out_r[2] <= irq_n_i;
76+
control_out_r[2] <= irq_n_i || !IRQ_OUT_ENABLE;
7577
end
7678
end
7779

@@ -273,7 +275,7 @@ module apple_bus #(
273275

274276
end
275277

276-
assign a2_bridge_bus_d_oe_n_o = !data_out_en_i;
278+
assign a2_bridge_bus_d_oe_n_o = ~(data_out_en_i & BUS_DATA_OUT_ENABLE);
277279

278280
assign a2bus_if.data_in_strobe = data_in_strobe_r;
279281

‎boards/a2n20v2/hdl/top.sv

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,9 @@ module top #(
190190
);
191191

192192
apple_bus #(
193-
.CLOCK_SPEED_HZ(CLOCK_SPEED_HZ)
193+
.CLOCK_SPEED_HZ(CLOCK_SPEED_HZ),
194+
.BUS_DATA_OUT_ENABLE(BUS_DATA_OUT_ENABLE),
195+
.IRQ_OUT_ENABLE(IRQ_OUT_ENABLE)
194196
) apple_bus (
195197
.a2bus_if(a2bus_if),
196198

@@ -450,7 +452,7 @@ module top #(
450452

451453
// Interrupts
452454

453-
assign irq_n_w = (mb_irq_n && vdp_irq_n && ssc_irq_n) || !IRQ_OUT_ENABLE;
455+
assign irq_n_w = mb_irq_n && vdp_irq_n && ssc_irq_n;
454456

455457
// Audio
456458

‎boards/a2n20v2/impl/a2n20v2_process_config.json

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,88 @@
1+
{
2+
"BACKGROUND_PROGRAMMING" : "off",
3+
"COMPRESS" : false,
4+
"CPU" : false,
5+
"CRC_CHECK" : true,
6+
"Clock_Route_Order" : 0,
7+
"Correct_Hold_Violation" : true,
8+
"DONE" : false,
9+
"DOWNLOAD_SPEED" : "default",
10+
"Disable_Insert_Pad" : false,
11+
"ENABLE_CTP" : false,
12+
"ENABLE_MERGE_MODE" : false,
13+
"ENCRYPTION_KEY" : false,
14+
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
15+
"ERROR_DECTION_AND_CORRECTION" : false,
16+
"ERROR_DECTION_ONLY" : false,
17+
"ERROR_INJECTION" : false,
18+
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
19+
"Enable_DSRM" : false,
20+
"FORMAT" : "binary",
21+
"FREQUENCY_DIVIDER" : "",
22+
"Generate_Constraint_File_of_Ports" : false,
23+
"Generate_IBIS_File" : false,
24+
"Generate_Plain_Text_Timing_Report" : false,
25+
"Generate_Post_PNR_Simulation_Model_File" : false,
26+
"Generate_Post_Place_File" : false,
27+
"Generate_SDF_File" : false,
28+
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
29+
"Global_Freq" : "default",
30+
"GwSyn_Loop_Limit" : 2000,
31+
"HOTBOOT" : false,
32+
"I2C" : false,
33+
"I2C_SLAVE_ADDR" : "00",
34+
"IncludePath" : [
35+
36+
],
37+
"Incremental_Compile" : "",
38+
"Initialize_Primitives" : false,
39+
"JTAG" : false,
40+
"MODE_IO" : false,
41+
"MSPI" : true,
42+
"MSPI_JUMP" : false,
43+
"MULTIBOOT_ADDRESS_WIDTH" : "24",
44+
"MULTIBOOT_MODE" : "Normal",
45+
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
46+
"MULTIJUMP_ADDRESS_WIDTH" : "24",
47+
"MULTIJUMP_MODE" : "Normal",
48+
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
49+
"Multi_Boot" : true,
50+
"OUTPUT_BASE_NAME" : "a2n20v2",
51+
"POWER_ON_RESET_MONITOR" : true,
52+
"PRINT_BSRAM_VALUE" : true,
53+
"PROGRAM_DONE_BYPASS" : false,
54+
"PlaceInRegToIob" : true,
55+
"PlaceIoRegToIob" : true,
56+
"PlaceOutRegToIob" : true,
57+
"Place_Option" : "0",
58+
"Process_Configuration_Verion" : "1.0",
59+
"Promote_Physical_Constraint_Warning_to_Error" : true,
60+
"READY" : false,
61+
"RECONFIG_N" : false,
62+
"Ram_RW_Check" : true,
63+
"Replicate_Resources" : false,
64+
"Report_Auto-Placed_Io_Information" : false,
65+
"Route_Maxfan" : 23,
66+
"Route_Option" : "1",
67+
"Run_Timing_Driven" : true,
68+
"SECURE_MODE" : false,
69+
"SECURITY_BIT" : true,
70+
"SEU_HANDLER" : false,
71+
"SEU_HANDLER_CHECKSUM" : false,
72+
"SEU_HANDLER_MODE" : "auto",
73+
"SSPI" : true,
74+
"STOP_SEU_HANDLER" : false,
75+
"Show_All_Warnings" : false,
76+
"Synthesize_tool" : "GowinSyn",
77+
"TclPre" : "",
78+
"TopModule" : "top",
79+
"USERCODE" : "default",
80+
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
81+
"VCCAUX" : 3.3,
82+
"VCCX" : "3.3",
83+
"VHDL_Standard" : "VHDL_Std_1993",
84+
"Verilog_Standard" : "Vlg_Std_Sysv2017",
85+
"WAKE_UP" : "0",
86+
"show_all_warnings" : true,
87+
"turn_off_bg" : false
88+
}

‎boards/a2n20v2/impl/pnr/a2n20v2.fs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
//SecureMode: OFF
1818
//JTAGAsRegularIO: OFF
1919
//MultiBootSPIAddr: 0x00000000
20-
//Created Time: Thu Apr 25 19:06:28 2024
20+
//Created Time: Wed Jun 19 15:03:31 2024
2121
1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
2222
1111111111111111
2323
1010010111000011

‎boards/a2n20v2/impl/pnr/a2n20v2.pin.html

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ <h1><a name="Message">Pin Messages</a></h1>
7878
</tr>
7979
<tr>
8080
<td class="label">Created Time</td>
81-
<td>Thu Apr 25 19:06:29 2024
81+
<td>Wed Jun 19 15:03:33 2024
8282
</td>
8383
</tr>
8484
<tr>

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