AXISPACKER generating extreme timing paths

[KireinaHoro]

I'm trying to integrate the AXISPACKER IP core into my design, after a couple stages of header extraction modules that I wrote myself. I instantiated the IP core for a bus width of 512b on Xilinx UltraScale+, clocked at 250 MHz.

I'm observing extremely long combinatorial paths in the core of a whopping 56 stages:

Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) :        -16.734ns  (required time - arrival time)
  Source:                 i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.REG_OUTPUT.ro_valid_reg_rep__0/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/beat_skd/LOGIC.REG_OUTPUT.o_data_reg[418]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             clk_out1_design_1_clk_wiz_0_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (clk_out1_design_1_clk_wiz_0_0 rise@4.000ns - clk_out1_design_1_clk_wiz_0_0 rise@0.000ns)
  Data Path Delay:        21.141ns  (logic 5.491ns (25.974%)  route 15.650ns (74.026%))
  Logic Levels:           56  (LUT4=10 LUT5=4 LUT6=42)
  Clock Path Skew:        0.443ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.664ns = ( 10.664 - 4.000 ) 
    Source Clock Delay      (SCD):    6.061ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.794ns (routing 1.333ns, distribution 1.461ns)
  Clock Net Delay (Destination): 3.069ns (routing 1.211ns, distribution 1.858ns)

    Location             Delay type                Incr(ns)  Path(ns)    Partition      PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    -------------------------------------------------------
                         (clock clk_out1_design_1_clk_wiz_0_0 rise edge)
                                                      0.000     0.000 r                                      
    AY26                                              0.000     0.000 r  reconfigurable                      F_PRGC0_CLK_P (IN)
                         net (fo=0)                   0.100     0.100    reconfigurable                      i_app/i_eci_gateway/i_prgc0/I
    HPIOBDIFFINBUF_X1Y154
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.474     0.574 r  reconfigurable pblock_dynamic       i_app/i_eci_gateway/i_prgc0/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.624    reconfigurable                      i_app/i_eci_gateway/i_prgc0/OUT
    AY26                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.624 r  reconfigurable pblock_dynamic       i_app/i_eci_gateway/i_prgc0/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.335     0.959    reconfigurable                      i_app/i_eci_gateway/i_prgc0_n_0
    BUFGCE_X1Y148        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.987 r  reconfigurable pblock_dynamic       i_app/i_eci_gateway/i_clk_io_bufg/O
                         net (fo=25736, routed)       2.140     3.127    reconfigurable                      i_app/design_1_i/clk_wiz_0/inst/clk_in1
    MMCM_X1Y6            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.000 r  reconfigurable pblock_dynamic       i_app/design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.239     3.239    reconfigurable                      i_app/design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_0
    BUFGCE_X1Y149        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.267 r  reconfigurable pblock_dynamic       i_app/design_1_i/clk_wiz_0/inst/clkout1_buf/O
    X2Y9 (CLOCK_ROOT)    net (fo=213082, routed)      2.794     6.061    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/app_clk
    SLICE_X73Y352        FDRE                                         r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.REG_OUTPUT.ro_valid_reg_rep__0/C
  -------------------------------------------------------------------    -------------------------------------------------------
    SLICE_X73Y352        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.070     6.131 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.REG_OUTPUT.ro_valid_reg_rep__0/Q
                         net (fo=4, routed)           0.119     6.250    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.REG_OUTPUT.ro_valid_reg_rep__0_n_0
    SLICE_X73Y352        LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.133     6.383 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2126/O
                         net (fo=10, routed)          0.101     6.484    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2126_n_0
    SLICE_X73Y351        LUT6 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.047     6.531 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2130/O
                         net (fo=8, routed)           0.251     6.781    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2130_n_0
    SLICE_X73Y350        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.031     6.812 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2605/O
                         net (fo=22, routed)          0.193     7.006    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2605_n_0
    SLICE_X73Y348        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     7.095 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2443/O
                         net (fo=13, routed)          0.319     7.414    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2443_n_0
    SLICE_X74Y347        LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.088     7.502 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2310/O
                         net (fo=28, routed)          0.112     7.614    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2310_n_0
    SLICE_X74Y349        LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.114     7.728 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2302/O
                         net (fo=14, routed)          0.218     7.946    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2302_n_0
    SLICE_X74Y345        LUT5 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.081     8.027 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2321/O
                         net (fo=24, routed)          0.229     8.256    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2321_n_0
    SLICE_X75Y343        LUT4 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.114     8.370 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2489/O
                         net (fo=24, routed)          0.248     8.618    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2489_n_0
    SLICE_X74Y342        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.081     8.699 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2594/O
                         net (fo=24, routed)          0.303     9.002    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2594_n_0
    SLICE_X76Y338        LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.115     9.117 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2587/O
                         net (fo=15, routed)          0.146     9.263    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2587_n_0
    SLICE_X76Y337        LUT6 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.136     9.399 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2655/O
                         net (fo=22, routed)          0.251     9.650    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2655_n_0
    SLICE_X79Y336        LUT6 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.089     9.739 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2508/O
                         net (fo=14, routed)          0.265    10.004    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2508_n_0
    SLICE_X81Y334        LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.081    10.085 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2530/O
                         net (fo=2, routed)           0.201    10.287    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2530_n_0
    SLICE_X80Y332        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088    10.375 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2357/O
                         net (fo=22, routed)          0.179    10.554    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2357_n_0
    SLICE_X81Y332        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.114    10.668 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2251/O
                         net (fo=23, routed)          0.328    10.996    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2251_n_0
    SLICE_X83Y328        LUT4 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.114    11.110 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2553/O
                         net (fo=8, routed)           0.278    11.388    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2553_n_0
    SLICE_X85Y325        LUT6 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.135    11.523 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2381/O
                         net (fo=22, routed)          0.377    11.900    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2381_n_0
    SLICE_X88Y326        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.134    12.034 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2561/O
                         net (fo=1, routed)           0.180    12.214    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2561_n_0
    SLICE_X89Y323        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.114    12.328 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2387/O
                         net (fo=20, routed)          0.171    12.499    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2387_n_0
    SLICE_X91Y321        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.081    12.580 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2241/O
                         net (fo=18, routed)          0.300    12.880    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[639]_i_2241_n_0
    SLICE_X93Y319        LUT6 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.135    13.015 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_853/O
                         net (fo=12, routed)          0.405    13.420    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_853_n_0
    SLICE_X96Y318        LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.088    13.508 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_795/O
                         net (fo=22, routed)          0.119    13.627    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_795_n_0
    SLICE_X96Y317        LUT4 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.135    13.762 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_720/O
                         net (fo=29, routed)          0.406    14.167    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_720_n_0
    SLICE_X102Y314       LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.114    14.281 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_647/O
                         net (fo=22, routed)          0.355    14.637    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_647_n_0
    SLICE_X107Y313       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.115    14.752 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_619/O
                         net (fo=15, routed)          0.121    14.873    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_619_n_0
    SLICE_X106Y314       LUT4 (Prop_E6LUT_SLICEL_I3_O)
                                                      0.134    15.007 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_532/O
                         net (fo=27, routed)          0.288    15.295    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_532_n_0
    SLICE_X111Y315       LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.089    15.384 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_461/O
                         net (fo=25, routed)          0.777    16.160    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_461_n_0
    SLICE_X120Y311       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.134    16.294 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_409/O
                         net (fo=8, routed)           0.344    16.638    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_409_n_0
    SLICE_X122Y310       LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.082    16.720 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_395/O
                         net (fo=22, routed)          0.304    17.024    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_395_n_0
    SLICE_X125Y309       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.088    17.112 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_326/O
                         net (fo=2, routed)           0.238    17.350    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_326_n_0
    SLICE_X127Y308       LUT6 (Prop_A6LUT_SLICEM_I5_O)
                                                      0.136    17.486 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_267/O
                         net (fo=22, routed)          0.268    17.754    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_267_n_0
    SLICE_X131Y312       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.081    17.835 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[144]_i_236/O
                         net (fo=22, routed)          0.219    18.054    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[144]_i_236_n_0
    SLICE_X134Y311       LUT4 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.114    18.168 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[144]_i_194/O
                         net (fo=8, routed)           0.302    18.471    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[144]_i_194_n_0
    SLICE_X138Y311       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.113    18.584 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_116/O
                         net (fo=22, routed)          0.400    18.984    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_116_n_0
    SLICE_X143Y312       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.047    19.031 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_86/O
                         net (fo=22, routed)          0.123    19.153    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[136]_i_86_n_0
    SLICE_X142Y312       LUT6 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.136    19.289 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[144]_i_102/O
                         net (fo=14, routed)          0.354    19.644    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[144]_i_102_n_0
    SLICE_X146Y315       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.047    19.691 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[168]_i_125/O
                         net (fo=30, routed)          0.237    19.928    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[168]_i_125_n_0
    SLICE_X146Y325       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.133    20.061 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[200]_i_124/O
                         net (fo=22, routed)          0.285    20.346    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[200]_i_124_n_0
    SLICE_X151Y324       LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.090    20.436 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[200]_i_104/O
                         net (fo=32, routed)          0.227    20.662    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[200]_i_104_n_0
    SLICE_X151Y321       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.047    20.709 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[8]_i_15/O
                         net (fo=14, routed)          0.231    20.940    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[8]_i_15_n_0
    SLICE_X152Y326       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.090    21.030 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[11]_i_25/O
                         net (fo=30, routed)          0.210    21.240    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[11]_i_25_n_0
    SLICE_X152Y331       LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.136    21.376 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[14]_i_34/O
                         net (fo=30, routed)          0.621    21.998    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[14]_i_34_n_0
    SLICE_X158Y332       LUT4 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.081    22.079 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[14]_i_24/O
                         net (fo=9, routed)           0.162    22.241    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[14]_i_24_n_0
    SLICE_X157Y332       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.089    22.330 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[17]_i_14_replica/O
                         net (fo=6, routed)           0.476    22.806    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[17]_i_14_n_0_repN
    SLICE_X155Y338       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.049    22.855 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[20]_i_14/O
                         net (fo=30, routed)          0.173    23.027    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[20]_i_14_n_0
    SLICE_X155Y340       LUT6 (Prop_A6LUT_SLICEL_I5_O)
                                                      0.089    23.116 f  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[312]_i_15/O
                         net (fo=2, routed)           0.388    23.504    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[312]_i_15_n_0
    SLICE_X157Y340       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.133    23.637 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[23]_i_12/O
                         net (fo=38, routed)          0.541    24.178    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[23]_i_12_n_0
    SLICE_X156Y346       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.133    24.311 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[344]_i_32/O
                         net (fo=30, routed)          0.124    24.436    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[344]_i_32_n_0
    SLICE_X155Y346       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.047    24.483 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[368]_i_26/O
                         net (fo=22, routed)          0.468    24.951    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[368]_i_26_n_0
    SLICE_X147Y358       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.048    24.999 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[400]_i_20/O
                         net (fo=30, routed)          0.231    25.230    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[400]_i_20_n_0
    SLICE_X145Y359       LUT6 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.089    25.319 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[464]_i_6/O
                         net (fo=13, routed)          0.349    25.668    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[464]_i_6_n_0
    SLICE_X141Y372       LUT4 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.135    25.803 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[416]_i_12/O
                         net (fo=14, routed)          0.380    26.183    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[416]_i_12_n_0
    SLICE_X145Y357       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.047    26.230 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[442]_i_2/O
                         net (fo=5, routed)           0.364    26.595    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[442]_i_2_n_0
    SLICE_X140Y372       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.082    26.677 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[426]_i_2_replica/O
                         net (fo=4, routed)           0.173    26.850    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[426]_i_2_n_0_repN
    SLICE_X138Y372       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.047    26.897 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/slave_skd/LOGIC.r_data[418]_i_1_comp_1/O
                         net (fo=1, routed)           0.167    27.064    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/beat_skd/LOGIC.r_data[434]_i_1_0_repN_1_alias
    SLICE_X139Y372       LUT4 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.089    27.153 r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/beat_skd/skidbuffer__par_LUT4_560_comp/O
                         net (fo=1, routed)           0.049    27.202    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/beat_skd/p_0_in_0[418]
    SLICE_X139Y372       FDRE                                         r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/beat_skd/LOGIC.REG_OUTPUT.o_data_reg[418]/D
  -------------------------------------------------------------------    -------------------------------------------------------

                         (clock clk_out1_design_1_clk_wiz_0_0 rise edge)
                                                      4.000     4.000 r                                      
    AY26                                              0.000     4.000 r  reconfigurable                      F_PRGC0_CLK_P (IN)
                         net (fo=0)                   0.079     4.079    reconfigurable                      i_app/i_eci_gateway/i_prgc0/I
    HPIOBDIFFINBUF_X1Y154
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.418     4.497 r  reconfigurable pblock_dynamic       i_app/i_eci_gateway/i_prgc0/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     4.537    reconfigurable                      i_app/i_eci_gateway/i_prgc0/OUT
    AY26                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     4.537 r  reconfigurable pblock_dynamic       i_app/i_eci_gateway/i_prgc0/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.297     4.834    reconfigurable                      i_app/i_eci_gateway/i_prgc0_n_0
    BUFGCE_X1Y148        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.858 r  reconfigurable pblock_dynamic       i_app/i_eci_gateway/i_clk_io_bufg/O
                         net (fo=25736, routed)       1.943     6.801    reconfigurable                      i_app/design_1_i/clk_wiz_0/inst/clk_in1
    MMCM_X1Y6            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.560     7.361 r  reconfigurable pblock_dynamic       i_app/design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.210     7.571    reconfigurable                      i_app/design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_0
    BUFGCE_X1Y149        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.595 r  reconfigurable pblock_dynamic       i_app/design_1_i/clk_wiz_0/inst/clkout1_buf/O
    X2Y9 (CLOCK_ROOT)    net (fo=213082, routed)      3.069    10.664    reconfigurable                      i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/beat_skd/app_clk
    SLICE_X139Y372       FDRE                                         r  reconfigurable pblock_dynamic       i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/beat_skd/LOGIC.REG_OUTPUT.o_data_reg[418]/C
                         clock pessimism             -0.160    10.504                                            
                         clock uncertainty           -0.060    10.444                                            
    SLICE_X139Y372       FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.023    10.467    reconfigurable   pblock_dynamic         i_app/NicEngine_inst/AxiDmaPlugin_logic_packer/beat_skd/LOGIC.REG_OUTPUT.o_data_reg[418]
  -------------------------------------------------------------------
                         required time                         10.467                                            
                         arrival time                         -27.202                                            
  -------------------------------------------------------------------
                         slack                                -16.734                                            

LUT usage of the core is also (somewhat) surprising:

I'm not entirely sure what is causing this, and if there's a way around it. Can you take a look? Thanks a lot :)

[ZipCPU]

Yeah, sure ... let me take a look ...

[ZipCPU]

I'm showing a maximum logic depth of 9 for a data width of 32. How big is your data width?

[KireinaHoro]

I'm showing a maximum logic depth of 9 for a data width of 32. How big is your data width?

It's 512 bits -- I'm aware that this might expand the depth since it is in principle a fully connected barrel shifter, but not sure how much.

[ZipCPU]

Hmm ... is this a time sensitive task? Can you afford latency? You might need an application specific solution. I don't know. Yes, the current axispacker algorithm logic will bloom with a wide data width.

For the cost of (about) (512/8) or 64 (pipeline) clocks, you can adjust the logic so it first pushes everything to the right (towards the LSB), 8b at a time. A second stage could then merge words together using the full barrel shifter.

Can you share anything about the data you are working with that requires something like this?

[KireinaHoro]

For the cost of (about) (512/8) or 64 (pipeline) clocks, you can adjust the logic so it first pushes everything to the right (towards the LSB), 8b at a time. A second stage could then merge words together using the full barrel shifter.

This actually sounds a bit like how I implemented my header stripping module right now -- I do two count trailing zeroes to find the length of the contiguous segment without holes each cycle and update counters to see if I removed enough bytes. Difference is I'm not shifting data or TKEEP -- only clearing the relevant bits in TKEEP. The implementation is in SpinalHDL.

Can you share anything about the data you are working with that requires something like this?

I'm using the core inside a NIC that I'm building. The NIC takes RX packets from the Xilinx 100Gbps CMAC IP core that comes with a 512b datapath. I have a module to strip a fixed number of bytes off the start of the AXI-Stream (configurable at elaboration). The module strips the header by setting TKEEP to zero for the removed bytes, as I explained earlier.

I chain these modules to remove Ethernet headers, IP headers, UDP/TCP headers, etc. Eventually I end up with an AXI stream that has some number of NULL bytes at the beginning -- len(sum(headers)) % 64 to be exact. Since the packet might have travelled through different paths in the decoder pipeline, e.g. Ethernet - IP - TCP vs. Ethernet - IPv6 - UDP, the number of null bytes are not always fixed.

I think a design that splits into multiple stages and then merges them back sounds reasonable -- 8b at a time sounds a bit extreme, maybe 32b * 16 would still work fine? We could probably stick more logic into one stage (and still hit 250 MHz). If the design would be fully pipelined, 16 cycles of latency (~64ns) is not too much of an issue.

[ZipCPU]

Sounds to me like the "answer" to the AXISPACKER would be a bit of an algorithm rewrite, so that it packs data in stages.

As for network packet handling, have you considered using a (subtly) different protocol, like the AXI Network protocol? It would have a logic advantage over the AXI Stream protocol you are using, simply because it doesn't use the TKEEP but rather a BYTES feature. You can then dump your packet into something like a more conventional gearbox to pack things back together to the full bus width.