Normalizing buses of width 1 into wires

[donn]

Somewhere between 0.48 and 0.54 (quite a range, I know) Yosys stopped changing buses with the width [0:0] to just a wire in the final output netlist. For the record, I agree that this is the correct thing to do, but it's causing some unexpected ramifications in my PnR flow.

Just asking real quick if there's a quick way around this before I start bisecting.

[povik]

@donn #5095

I'm not sure there's a command flag to disable this but you can always strip the single_bit_vector attribute from all wires.

[donn]

Thanks for the quick response! Yeah, this will do nicely. Appreciated.

[donn]

For anyone reading in the future, literally just attrmap -remove single_bit_vector after hierarchy.