Unmapped Memories issue #5168
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Hello, I am trying to obtain a netlist out of the AES Verilog design found here: I am trying the following yosys script: read_verilog keyExpansion.v hierarchy -top AES flatten memory_collect memory_map proc; opt; techmap; opt write_blif aes.blif yosys finishes through everything and then throws the error "Found unmapped memories in module AES: unmapped memories are not supported in BLIF backend" I am new to Yosys and Verilog; I would really appreciate any advice on how to get Yosys to finish creating a netlist for me. Thanks! -Bryan |
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Replies: 2 comments 2 replies
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You need to run
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Thank you so much! That solved the problem. |
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You need to run
proc
before thememory_*
commands, if you check the log you'll see something like