How can I invert the output D bitwise in Verilog without modifying the original source file, and then output a new Verilog file

[yujning]

Is there a direct command to do this? Or should I add a wire? Or should I write another module and connect the two together?

[KrystalDelusion]

Provided the output you want to invert is connected to a wire (and not being directly driven as the output of a cell), you can do something like
in.v

module top(input [3:0] a, b, output [3:0] d);
	wire [3:0] d_temp;
	some_mod some_inst(.x(a), .y(b), .z(d));
	assign d = d_temp;
endmodule

yosys -p 'read_verilog in.v; insbuf -buf $_NOT_ A Y w:d; write_verilog -noattr out.v'
and get
out.v

/* Generated by Yosys 0.51+125 (git sha1 98d4355b8, ccache clang++ 18.1.8 -fPIC -O3) */

module top(a, b, d);
  input [3:0] a;
  wire [3:0] a;
  input [3:0] b;
  wire [3:0] b;
  output [3:0] d;
  wire [3:0] d;
  wire [3:0] d_temp;
  assign d[0] = ~d_temp[0];
  assign d[1] = ~d_temp[1];
  assign d[2] = ~d_temp[2];
  assign d[3] = ~d_temp[3];
  some_mod some_inst (
    .x(a),
    .y(b),
    .z(d)
  );
endmodule

The other option would be to write a wrapper module (and optionally rename the original so that your new top module is still called the same thing).

read_verilog in.v
rename top old_top
read_verilog << EOF
module top(input [3:0] a, b, output [3:0] n_d);
    wire [3:0] d;
    old_top old(.a(a), .b(b), .d(d));
    assign n_d = ~d;
endmodule
EOF
write_verilog -noattr out.v