[DFF Instance Naming] How to make DFF instance names follow the RTL names instead of being auto-generated (_14_, _15_, etc.)?

[ApeachM]

Environment

• Yosys version: 0.46 (git sha1 e97731b)
• OS: Ubuntu 22.04
• Invocation: yosys -s synth.ys

---

1. RTL Code

rtl/top.v

module top (
    input  wire       clk,
    input  wire       rst,
    input  wire       en,
    input  wire [3:0] d,
    output wire [3:0] q
);

    my_module u_my_module (
        .clk  (clk),
        .rst  (rst),
        .en   (en),
        .d    (d),
        .q    (q)
    );

endmodule

rtl/my_module.v

module my_module (
    input  wire       clk,
    input  wire       rst,
    input  wire       en,
    input  wire [3:0] d,
    output reg  [3:0] q
);

    always @(posedge clk or posedge rst) begin
        if (rst)
            q <= 4'h00;
        else if (en)    // “clock-gating candidate” enable condition
            q <= d;
    end

endmodule

---

2. Yosys Script

synth.ys

read_verilog rtl/top.v rtl/my_module.v
read_liberty -ignore_miss_func nangate45/NangateOpenCellLibrary.lib

# 1. Basic synthesis
synth -top top

# 2. Insert clock gating
clockgate -pos CLKGATE_X1 E:CK:GCK

# 3. Map DFFs to standard cells
dfflibmap -liberty nangate45/NangateOpenCellLibrary.lib

# 4. Logic optimization
abc -liberty nangate45/NangateOpenCellLibrary.lib

# 5. Clean up
opt_clean

# 6. BUS SPLIT + RENAMING
splitnets -ports
rename -wire -suffix _reg

# 7. Write out final netlist
write_verilog -noattr netlist.v

---

3. Actual Result (netlist.v snippet)

  CLKGATE_X1 _13_ (
    .CK(clk),
    .E(en),
    .GCK(_04_)
  );
  DFFR_X1 _14_ (
    .CK(_04_),
    .D(d[0]),
    .Q(q[0]),
    .QN(_08_),
    .RN(_00_)
  );
  DFFR_X1 _15_ (
    .CK(_04_),
    .D(d[1]),
    .Q(q[1]),
    .QN(_07_),
    .RN(_01_)
  );
  // … instances _16_, _17_ remain similarly unnamed

---

4. Expected Result

  CLKGATE_X1 gate_0 (
    .CK(clk),
    .E(en),
    .GCK(gated_clk)
  );
  DFFR_X1 q_0_reg (
    .CK(gated_clk),
    .D(d[0]),
    .Q(q[0]),
    .RN(rst)
  );
  DFFR_X1 q_1_reg (
    .CK(gated_clk),
    .D(d[1]),
    .Q(q[1]),
    .RN(rst)
  );
  // … and so on for q_2_reg, q_3_reg

---

5. What I’ve Tried

• splitnets -ports (to break buses into individual nets)
• rename -wire -suffix _reg
• rename -enumerate -pattern 'q_reg_%'
• rename -cell / rename -module variants
• Moving opt_clean before/after splitnets
• splitnets -nets vs. -ports

---

6. Questions

1. Why do DFF instances still keep autogenerated names (_14_, _15_, etc.) after splitnets -ports + rename -wire -suffix _reg?
2. Is there a different pass order, option, or command I should be using to have cell instance names follow the RTL signal names (e.g. q[0] → q_0_reg)?

Any pointers or example scripts to achieve the desired naming would be greatly appreciated. Thanks!

[KrystalDelusion]

splitnets -ports -format _; autoname should do q[0] → q_0 → q_0_DFFR_X1.

rename -wire checks that cells are only driving a single output port, but requires the cell definitions to be loaded. It also only works on cells where the output wire is not private (which abc generated wires are). But you should be able to do something like

# load library
read_liberty -lib -ignore_miss_func nangate45/NangateOpenCellLibrary.lib
# rename registers from wires
rename -wire -suffix _reg t:DFFR_X1

and that'll give you q[0]_reg.