Yosys $paramod issue

[qwera-web]

I’m using Yosys to generate a synthesized netlist for my design without applying the flatten command. As a result, Yosys creates parameterized module instances with $paramod prefixes. I’ve successfully used the rename command to change these module names; however, the instantiations still reference the original $paramod names, which leads to mismatches.

I'm exploring whether box_derive can help address this issue by generating named specializations of parameterized modules with more meaningful identifiers. If so, could you briefly explain how to use box_derive correctly to ensure that both the module definitions and their instantiations are consistently renamed?

[KrystalDelusion]

I haven't used it, but https://github.com/YosysHQ/yosys/blob/main/tests/various/box_derive.ys shows an example use of it. Looking at the source code, it only works on cells where the module is a blackbox or whitebox (because they are ignored by hierarchy naming things $paramod, so I suspect it's not what you're looking for).

[KrystalDelusion]

Also, $paramod names should only affect modules, not their instances (cells). Cell names should still be whatever they were named in the source. e.g.

yosys/docs/source/code_examples/fifo/fifo.v

Lines 43 to 49 in 6378ba1

	addr_gen #(.MAX_DATA(MAX_DATA))
	fifo_writer (
	.en (wen),
	.clk (clk),
	.rst (rst),
	.addr (waddr)
	);

Calling read_verilog fifo.v; hierarchy -top fifo creates a module named $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000, and a cell fifo/fifo_reader which references it:

yosys> dump fifo/fifo_reader
  attribute \src "fifo.v:52.2-57.3"
  cell $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000 \fifo_reader
    connect \addr \raddr
    connect \rst \rst
    connect \clk \clk
    connect \en \ren
  end

But it is still called fifo_reader, and the module name does at least include the original name addr_gen. What are you trying to do where that is insufficient?

[qwera-web]

thanks for your response but this is how my design looks
% ls

24 modules:
$paramod$0132d82664ec5574a1e366e06bd1625554150da4\ibex_csr
$paramod$03d7167f03644711119f23d592daee606cfebe0c\ibex_id_stage
$paramod$158245387f3da7ba82feb17eac9d69cbf948ebcd\ibex_ex_block
$paramod$16bd66fd1d1dbd7c4dd1efdb08bf1560b5c5007a\ibex_register_file_ff
$paramod$3d1c22e06fd74c9694bb6640561f8fd637f7a02e\ibex_if_stage
$paramod$410b37fbfbfa994790f1902c150d2be939cadb3b\ibex_csr
$paramod$4f46e25470a27719ee9ca03cee1a0827eff766f7\ibex_csr
$paramod$5714e31d82f2b8816750797f158ebea69a089104\ibex_csr
$paramod$798a254c6337829ae6c1a6eb733eb2413df9fff0\ibex_csr
$paramod$84261d804587eb0ae51174310d90890db16d9f6a\ibex_decoder
$paramod$9a435d8f6db004a67362aa9a56f32ea481a74dbe\ibex_csr
$paramod$9ea54a48cc9628bf1663475182d340b6fda961f1\ibex_csr
$paramod$bf1673a619f4567e800f57085f501f0331f04a7c\ibex_cs_registers
$paramod\ibex_alu\RV32B=s32'00000000000000000000000000000000
$paramod\ibex_controller\WritebackStage=1'0\BranchPredictor=1'0
$paramod\ibex_counter\CounterWidth=s32'00000000000000000000000001000000
$paramod\ibex_fetch_fifo\NUM_REQS=32'00000000000000000000000000000010
$paramod\ibex_multdiv_fast\RV32M=s32'00000000000000000000000000000010
$paramod\ibex_prefetch_buffer\BranchPredictor=1'0
$paramod\ibex_wb_stage\WritebackStage=1'0
ibex_compressed_decoder
ibex_core
ibex_load_store_unit
prim_clock_gating
and after entering in module $paramod$03d7167f03644711119f23d592daee606cfebe0c\ibex_id_stage
this is how my stat command looks
% stat

79. Printing statistics.

=== $paramod$03d7167f03644711119f23d592daee606cfebe0c\ibex_id_stage ===

Number of wires: 521
Number of wire bits: 1475
Number of public wires: 147
Number of public wire bits: 1101
Number of ports: 111
Number of port bits: 873
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 559
$paramod$84261d804587eb0ae51174310d90890db16d9f6a\ibex_decoder 1
$paramod\ibex_controller\WritebackStage=1'0\BranchPredictor=1'0 1
sky130_fd_sc_hd__a211oi_1 2
sky130_fd_sc_hd__a21oi_1 20
sky130_fd_sc_hd__a221oi_1 15
sky130_fd_sc_hd__a222oi_1 25
sky130_fd_sc_hd__a22oi_1 40
and in this you can see in cells i am getting $paramod naming so how can i change this name

[KrystalDelusion]

That's because you're looking at the module, not the cell. If you cd to e.g. ibex_core you should see the actual instances.

Again using the fifo example, if I ls with no selection I see

2 modules:
  $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
  fifo

And if I cd fifo; ls, then under cells I see

9 cells:
  $add$fifo.v:66$17
  $logic_and$fifo.v:65$16
  $logic_and$fifo.v:67$19
  $logic_not$fifo.v:65$15
  $logic_not$fifo.v:67$18
  $memrd$\data$fifo.v:39$13
  $sub$fifo.v:68$20
  fifo_reader
  fifo_writer

Which shows the named cell, fifo_reader and fifo_writer which are both instances of $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000, so calling stat will list 2 instances of that module. If you don't care about the number of cells reported by stat, you could use uniquify to convert each instance of the module into its own module, with the name derived from the hierarchy. e.g. uniquify; stat fifo

...
   Number of cells:                  9
     $add                            1
     $logic_and                      2
     $logic_not                      2
     $memrd                          1
     $sub                            1
     fifo.fifo_reader                1
     fifo.fifo_writer                1

[qwera-web]

thanks but i am trying to remove this $paramod naming can you suggest me better way because in my current approach i am doing ls and using rename command for these paramod modules but when i check stat command instantiation of these paramod naming module is still there with paramod prefix so i am having issue after using write_verilog command

[KrystalDelusion]

Does uniquify suit your use case?

[qwera-web]

partially yes

[qwera-web]

hello in your fifo.v example i tried also and after uniquify i am getting this:
% ls

4 modules:
$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
fifo
fifo.fifo_reader
fifo.fifo_writer
and now i am doing
write_verilog -noattr <file_name.v>
so in this file i am getting this:
module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000 (en, clk, rst, addr);
wire 00;
wire 01;
wire 02;
wire 03;
as you can see i am still getting paramod prefix so i want to fix this issue

[KrystalDelusion]

The $paramod module shouldn't be used if you've called uniquify and calling hierarchy again will remove it:

yosys> hierarchy

4. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `fifo'. Setting top module to fifo.

4.1. Analyzing design hierarchy..
Top module:  \fifo
Used module:     \fifo.fifo_reader
Used module:     \fifo.fifo_writer

4.2. Analyzing design hierarchy..
Top module:  \fifo
Used module:     \fifo.fifo_reader
Used module:     \fifo.fifo_writer
Removing unused module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.
Removed 1 unused modules.

yosys> ls

3 modules:
  fifo
  fifo.fifo_reader
  fifo.fifo_writer

[qwera-web]

sky130_fd_sc_hd__mux2_1 02 (
.A0(rf_wdata_lsu_i[8]),
.A1(rf_wdata_id_i[8]),
.S(rf_we_id_i),
.X(rf_wdata_wb_o[8])
);
sky130_fd_sc_hd__mux2_1 03 (
.A0(rf_wdata_lsu_i[9]),
.A1(rf_wdata_id_i[9]),
.S(rf_we_id_i),
.X(rf_wdata_wb_o[9])
hello can we change these [] to any other character?

[KrystalDelusion]

You could try the splitnets command https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/splitnets.html

[qwera-web]

\ibex_core.core_clock_gate_i core_clock_gate_i (
.clk_i(clk_i),
.clk_o(clk),
.en_i(clock_en),
.test_en_i(test_en_i)
);
this is the module :
module \ibex_core.core_clock_gate_i (clk_i, en_i, test_en_i, clk_o);
input clk_i;
wire clk_i;
output clk_o;
wire clk_o;
input en_i;
wire en_i;
input test_en_i;
wire test_en_i;
sky130_fd_sc_hd__and2_0 and2_0_0 (
.A(en_i),
.B(clk_i),
.X(clk_o)
);
endmodule
what actually i am trying is want to remove these . and in place of that i want to use x but issue comes i am using rename command here if i rename module it happens correctly but this is not changing automatically in instantiation so this is the issue i am getting please help or suggest any better way to do this

[KrystalDelusion]

Sorry, what are you trying to remove? If you are trying to replace a net with 'x you can use cutpoint -undef

[qwera-web]

I have a module lets say:
ibex_core.core_clock_gate_i and its instantiation is ibex_core.core_clock_gate_i ibex() so now i want to change this . To x so expected output is:
For module ibex_corexcore_clock_gate_i and for instantiation is ibex_corexcore_clock_gate_i ibex() so i tried rename and submod to change these but what happens is only module is changing . To x no change is showing in instantiation i want to change in both

[KrystalDelusion]

Ah I see, you want to replace the . in the module name with _. You might be able to use the chtype command?

...
rename mod.x mod_x
chtype -map mod.x mod_x
...

[qwera-web]

thanks it is working

[qwera-web]

hello i am creating netlist but at the end i am still getting these conditional conditions
assign net_1883 = raddr[0] ? datax105x[6] : datax104x[6];
assign net_1884 = raddr[0] ? datax107x[6] : datax106x[6];
assign net_1885 = raddr[1] ? net_1884 : net_1883;
assign net_1886 = raddr[0] ? datax109x[6] : datax108x[6];
assign net_1887 = raddr[0] ? datax111x[6] : datax110x[6];
assign net_1888 = raddr[1] ? net_1887 : net_1886;
assign net_1889 = raddr[2] ? net_1888 : net_1885;
assign net_1890 = raddr[3] ? net_1889 : net_1882;
assign net_1891 = raddr[0] ? datax113x[6] : datax112x[6];
how can i remove or change them

[KrystalDelusion]

Can you please provide more context about the commands/design you're using, and open a new discussion for it instead of reusing this one.