Techmap blackbox port direction

[ben-j-c]

I'm working on a project. I'm trying to use Yosys to compile verilog to coarse cells which I then simulate. Here I want to extract 32-bit multiplications and perform them in an optimized way. Looking at the json the port names and directions are wrong. I see a suspect "module_not_derived," but I dont quite understand how to address that hint.

Am I even using the right tool?

Ideally I want to replace $mul with a blackbox that my simulator can quickly identify and then do different transformations for non-conforming multiplications.

Heres my script, test1.ys.

read_verilog test1.v
#read_verilog -lib ../techmap/v2f_techmap.v
hierarchy -check -top top
flatten
proc
opt
techmap -map ../techmap/v2f_techmap.v;;
write_json -selected ./output/test1.json
show -lib ../techmap/v2f_techmap.v

test1.v

module top(
	input signed [31:0] signal_0,
	input signed [31:0] signal_1,
	output reg [31:0] signal_2
);
	always @(*) begin
		signal_2 = signal_0*signal_1;
	end
endmodule

../techmap/v2f_techmap.v

(* blackbox, keep *)
module v2f_mul (A,B,Y);
	parameter A_WIDTH = 32; parameter B_WIDTH = 32; parameter Y_WIDTH = 32;
	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	input [A_WIDTH-1:0] A;
	input [B_WIDTH-1:0] B;
	output [Y_WIDTH-1:0] Y;
	//assign Y = A*B;
endmodule

(* techmap_celltype = "$mul" *)
module v2f_rule_mul (A, B, Y);
	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 1;
	parameter B_WIDTH = 1;
	parameter Y_WIDTH = 1;

	input [A_WIDTH-1:0] A;
	input [B_WIDTH-1:0] B;
	output [Y_WIDTH-1:0] Y;

	wire _TECHMAP_FAIL_ = A_WIDTH > 32 || B_WIDTH > 32 || Y_WIDTH > 32;
	(*keep*) v2f_mul #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .B_SIGNED(B_SIGNED), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_(A, B, Y);
endmodule

// Omitted irrelevant rules

Relevant json section:

"top": {
"cells": {
        "$mul$test1.v:7$2": {
          "hide_name": 1,
          "type": "v2f_mul",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000001",
            "A_WIDTH": "00000000000000000000000000100000",
            "B_SIGNED": "00000000000000000000000000000001",
            "B_WIDTH": "00000000000000000000000000100000",
            "Y_WIDTH": "00000000000000000000000000100000"
          },
          "attributes": {
            "keep": "00000000000000000000000000000001",
            "module_not_derived": "00000000000000000000000000000001",
            "src": "test1.v:7.14-7.31|../techmap/v2f_techmap.v:79.120-79.146"
          },
          "connections": {
            "$1": [ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 ],
            "$2": [ 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65 ],
            "$3": [ 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97 ]
          }
        }
      },
}

executing yosys -g -s test1.ys

yosys -s ./test1.ys -g

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.52 (git sha1 fee39a328, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)

-- Executing script file `./test1.ys' --

1. Executing Verilog-2005 frontend: test1.v
Parsing Verilog input from `test1.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \top

2.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

3. Executing FLATTEN pass (flatten design).

4. Executing PROC pass (convert processes to netlists).

4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 1 assignment to connection.

4.4. Executing PROC_INIT pass (extract init attributes).

4.5. Executing PROC_ARST pass (detect async resets in processes).

4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top.$proc$test1.v:6$1'.

4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\top.\signal_2' from process `\top.$proc$test1.v:6$1'.

4.9. Executing PROC_DFF pass (convert process syncs to FFs).

4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$proc$test1.v:6$1'.
Cleaned up 0 empty switches.

4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

5. Executing OPT pass (performing simple optimizations).

5.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

5.6. Executing OPT_DFF pass (perform DFF optimizations).

5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
  removing unused non-port wire $0\signal_2[31:0].
  removing unused non-port wire $mul$test1.v:7$2_Y.
Removed 0 unused cells and 2 unused wires.

5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

5.9. Rerunning OPT passes. (Maybe there is more to do..)

5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

5.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

5.13. Executing OPT_DFF pass (perform DFF optimizations).

5.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

5.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

5.16. Finished OPT passes. (There is nothing left to do.)

6. Executing TECHMAP pass (map to technology primitives).

6.1. Executing Verilog-2005 frontend: ../techmap/v2f_techmap.v
Parsing Verilog input from `../techmap/v2f_techmap.v' to AST representation.
Generating RTLIL representation for module `\v2f_mul'.
Generating RTLIL representation for module `\v2f_rule_reduce_and'.
Generating RTLIL representation for module `\v2f_rule_reduce_or'.
Generating RTLIL representation for module `\v2f_rule_add'.
Generating RTLIL representation for module `\v2f_rule_sub'.
Generating RTLIL representation for module `\v2f_rule_mul'.
Generating RTLIL representation for module `\v2f_rule_div'.
Generating RTLIL representation for module `\v2f_rule_mod'.
Generating RTLIL representation for module `\v2f_rule_and'.
Generating RTLIL representation for module `\v2f_rule_or'.
Generating RTLIL representation for module `\v2f_rule_xor'.
Generating RTLIL representation for module `\v2f_rule_shr'.
Generating RTLIL representation for module `\v2f_rule_shl'.
Generating RTLIL representation for module `\v2f_rule_not'.
Generating RTLIL representation for module `\v2f_rule_gt'.
Generating RTLIL representation for module `\v2f_rule_lt'.
Generating RTLIL representation for module `\v2f_rule_ge'.
Generating RTLIL representation for module `\v2f_rule_le'.
Generating RTLIL representation for module `\v2f_rule_eq'.
Generating RTLIL representation for module `\v2f_rule_ne'.
Successfully finished Verilog frontend.

6.2. Continuing TECHMAP pass.
Cell type mappings to use:
    v2f_mul: v2f_mul
    $reduce_and: v2f_rule_reduce_and
    $reduce_or: v2f_rule_reduce_or
    $add: v2f_rule_add
    $sub: v2f_rule_sub
    $mul: v2f_rule_mul
    $div: v2f_rule_div
    $mod: v2f_rule_mod
    $and: v2f_rule_and
    $or: v2f_rule_or
    $xor: v2f_rule_xor
    $shr: v2f_rule_shr
    $shl: v2f_rule_shl
    $not: v2f_rule_not
    $gt: v2f_rule_gt
    $lt: v2f_rule_lt
    $ge: v2f_rule_ge
    $le: v2f_rule_le
    $eq: v2f_rule_eq
    $ne: v2f_rule_ne

Parameter \A_SIGNED = 1
Parameter \B_SIGNED = 1
Parameter \A_WIDTH = 32
Parameter \B_WIDTH = 32
Parameter \Y_WIDTH = 32

6.3. Executing AST frontend in derive mode using pre-parsed AST for module `\v2f_rule_mul'.
Parameter \A_SIGNED = 1
Parameter \B_SIGNED = 1
Parameter \A_WIDTH = 32
Parameter \B_WIDTH = 32
Parameter \Y_WIDTH = 32
Generating RTLIL representation for module `$paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\v2f_rule_mul'.

6.4. Continuing TECHMAP pass.
Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\v2f_rule_mul for cells of type $mul.
Mapping top.$mul$test1.v:7$2 ($mul) using $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\v2f_rule_mul.
No more expansions possible.
Finding unused cells or wires in module \top..
  removing unused non-port wire $techmap3$mul$test1.v:7$2._TECHMAP_FAIL_.
  removing unused non-port wire $techmap3$mul$test1.v:7$2.Y.
  removing unused non-port wire $techmap3$mul$test1.v:7$2.B.
  removing unused non-port wire $techmap3$mul$test1.v:7$2.A.
Removed 0 unused cells and 4 unused wires.

7. Executing JSON backend.

8. Generating Graphviz representation of design.
Writing dot description to `/home/ben/.yosys_show.dot'.
Dumping module top to page 1.
Exec: { test -f '/home/ben/.yosys_show.dot.pid' && fuser -s '/home/ben/.yosys_show.dot.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '/home/ben/.yosys_show.dot'; ) 3> '/home/ben/.yosys_show.dot.pid' &

End of script. Logfile hash: 74a6bcd6d1, CPU: user 0.01s system 0.01s, MEM: 18.75 MB peak
Yosys 0.52 (git sha1 fee39a328, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)
Time spent: 30% 3x read_verilog (0 sec), 21% 4x opt_expr (0 sec), ...

Thanks in advance for any help you can provide!

[KrystalDelusion]

The module_not_derived attribute is because the v2f_mul module is a blackbox. which I think is also related to the missing port directions (sidenote that the show output connects them all on the left not because they're all inputs, but just because that's the default side when the direction isn't known).

The unnamed ports is because _TECHMAP_REPLACE_ doesn't work with positional arguments.

You also typically want to provide the cell model and the techmap rules in separate files, i.e.
v2f_model.v

module v2f_mul (A,B,Y);
	parameter A_WIDTH = 32; parameter B_WIDTH = 32; parameter Y_WIDTH = 32;
	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	input [A_WIDTH-1:0] A;
	input [B_WIDTH-1:0] B;
	output [Y_WIDTH-1:0] Y;
	assign Y = A*B;
endmodule

which lets you drop the blackbox and keep attributes, since they're automatically added by the -lib, while still having the Y = A*B assignment which makes for a circular definition if you had it in the same file as the techmap rule.

v2f_techmap.v

(* techmap_celltype = "$mul" *)
module v2f_rule_mul (A, B, Y);
	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 1;
	parameter B_WIDTH = 1;
	parameter Y_WIDTH = 1;

	input [A_WIDTH-1:0] A;
	input [B_WIDTH-1:0] B;
	output [Y_WIDTH-1:0] Y;

	wire _TECHMAP_FAIL_ = A_WIDTH > 32 || B_WIDTH > 32 || Y_WIDTH > 32;
	(*keep*) v2f_mul #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .B_SIGNED(B_SIGNED), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_(.A(A), .B(B), .Y(Y));
endmodule

And then in your script:

read_verilog -icells test1.v
read_verilog -lib v2f_model.v
hierarchy -check -top top
flatten
proc
opt
techmap -map v2f_techmap.v;;
write_json -selected -
show

note that if you don't provide the -lib v2f_model.v either as a read_verilog or in the show command you'll get A B and Y ports all on the left of the v2f_mul, but even with the lib the v2f_mul is still flagged with module_not_derived, so that is probably unrelated to the directions. And if you don't provide it with read_verilog then the json output will be missing port directions.

[ben-j-c]

Thanks! The json looks exactly like what I wanted.

The biggest problem for me was just the positional arguments.