Setting Fanout limitation for synthesis - HELP!!

[alensebastian7]

While using Yosys for synthesis for digital design flow, the tool by default fixes fanouts and later optimizes it according to the capacitive load set ( but this also doesn't seem to work properly). For my custom technology, the output is also a current load and thus fanout should be limited to maximum 4 for all cells. ( Higher strength cell and buffer insertion is not a solution). Is there any way for me to set this fanout limit?
i tried different options, but nothing seem to work

[QuantamHD]

Are you doing an ASIC or FPGA?

[alensebastian7]

Its an ASIC design for a non-Silicon technology (hence the additional constraints). I need to tapeout this circuit and make it work.