Issues Instantiating Yosys Verilog

[ChrisLalloMiami]

Hi, sorry if this is the wrong place for this post. I have a Verilog module being written by Yosys. The interface of the original module looks something like module my_module(program_address[31:0], ...), but when checking the Verilog file created by Yosys, it looks like module my_module(\program_address[0] , \program_address[1] , ...). I have verified that this new file compiles, but I am having issues instantiating the module. I have tried using both ordered and named ports, providing individual bits and entire buses, etc., but I have not had any success. Does anyone know how it should be done?

[KrystalDelusion]

What are you doing between reading the verilog input and writing the verilog output?