Synthesis support for $countones?

[hankhsu1996]

I'm new to Yosys and considering it as an alternative synthesis tool. The main issue I'm facing is the lack of synthesis support for $countones. This primitive is supported in Synopsys-based flows like Design Compiler and Synplify.

Is there any existing support or workaround for $countones in Yosys (like plugin, etc)? Any guidance on how to approach this would be greatly appreciated.

[KrystalDelusion]

It appears to work for me

read_verilog <<EOF
module top (input [3:0] a, output [3:0] b);

assign b = $countones(a);

endmodule
EOF

synth

gives

...
2.25. Printing statistics.

=== top ===

   Number of wires:                  9
   Number of wire bits:             15
   Number of public wires:           2
   Number of public wire bits:       8
   Number of ports:                  2
   Number of port bits:              8
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 10
     $_ANDNOT_                       2
     $_AND_                          1
     $_NOT_                          1
     $_OR_                           2
     $_XNOR_                         2
     $_XOR_                          2

[hankhsu1996]

Oops! I used the slang frontend (https://github.com/povik/yosys-slang) to read the Verilog, which likely caused the issue. Thanks for the clarification!