how can I map my RTL code for 16x16 memory using only NAND gate

[AbdulAhad36]

so basically I was synthesizing my 16x16 using cmos_cells.lib and I did it successfully usign cmos_cells.lib . Now I wanted to make a purely NAND netlist of the same code , I tried by removing all the other gate modules except the NAND part and then tried synthesizing it but when I ran the abc command the synthesing crashed and exited Yosys . what changes can I do in the abc algorithm or liberty file to make this work or is just me entering the wrong commands .

P.s. I am new to Yosys :)

[KrystalDelusion]

Can you share a reproducer? Design source code, Yosys script, and cell library.