Why does ROM take so many LUTs on iCE40UP?

[spth]

According to Lattice documentation, a LUT is a 16x1 ROM.
Now, I have a Verilog module for a ROM with one 16-bit and one 24-bit read port. This doesn't match the embedded block RAM well, so it gets synthesized to LUTs. That ROM gets its content via readmemh.

I tried with two data files, a 195B and a 255B one.

Naively, I would assume that I need 0.5 LUTs per Byte, and then a few more LUTs for the address decoders.
However, yosys 0.38 uses 809 LUTs for the 195B ROM, and 1345 LUTs for the 255B ROM, i.e. about 4.1 to 5.3 LUTs per Byte total.

That seems a lot to me. What am I missing? Are that many LUTs really needed? Could yosys do better? Could I rewrite my Verilog code for yosys to do better?

module rom(iread_addr, iread_data, iread_valid, dread_addr, dread_data, clk);
	parameter ROMSIZE = 512;
	parameter logic [15:0] ROMBASE = 16'h4000;

	input [15 : 0] iread_addr;
	output reg [23 : 0] iread_data;
	output reg iread_valid;
	input [15 : 0] dread_addr;
	output reg [15 : 0] dread_data;
	input clk;

	logic [15:0] dread_addr_rombased;

	reg [7:0] rom[ROMSIZE - 1 : 0];

	logic [15:0] iread_addr_rombased;

	assign iread_addr_rombased = iread_addr - ROMBASE;
	assign dread_addr_rombased = dread_addr - ROMBASE;

	initial $readmemh("test.vmem", rom);
		
	always @(posedge clk)
	begin
		iread_data[7 : 0] <= rom[iread_addr_rombased];
		iread_data[15 : 8] <= rom[iread_addr_rombased + 1];
		iread_data[23 : 16] <= rom[iread_addr_rombased + 2];
		dread_data[7:0] <= rom [dread_addr_rombased];
		dread_data[15:8] <= rom [dread_addr_rombased + 1];
		iread_valid <= 1;
	end
endmodule

[povik]

Can you attach some sample test.vmem contents?

[spth]

I guess one could separate the ROMs for odd vs. even addresses, then replicating each one three instead of five times would be sufficient. Though I have no idea if it would be reasonable to do so in yosys vs. in my code (I already did the same for my RAM, where I use on iCE40 block RAM each for odd and even addresses).

Also: if the memory gets replicated five times anyway (one copy for each read port), why not use embedded block RAMs instead of LUTs?

[povik]

Also: if the memory gets replicated five times anyway (one copy for each read port), why not use embedded block RAMs instead of LUTs?

Good question, it appears we have a bug which is that we don't factor in the number of replicas when estimating the cost of the ROM when implemented with LUTs.

[povik]

That still amounts to a number of LUTs per one replica that's too high though.

On second look it's not high. You should expect 0.5 LUTs per byte to hold the data, and then about the same number of LUTs for the muxing logic. So that works out to roughly one LUT per byte per replica, lower if there are exploitable patterns in the data, which is in agreement with what you see.

[spth]

Can I somehow hint yosys to use block RAM for this ROM? My SoC design currently uses 2 out of the 30 block RAMs on the iCE40UP5K, but with the 255B data file for the ROM it doesn't fit due to lack of LUTs.

P.S.: (* ram_style = "block" *) worked for me.

[povik]

(* ram_style = "block" *) worked for me.

Yes, that's the way to do it. There are other names for the attribute, they all do the same.