Yosys not mapping verilog to pdk lib file used

[tmaddali]

I am using the sky130_fd_sc_hd__tt_025C_1v80.lib file and I am running

abc -liberty sky130_fd_sc_hd__tt_025C_1v80.lib

after reading the verilog file. However, I run into this message when I run that command

2. Executing ABC pass (technology mapping using ABC).
   Skipping module riscv_exec as it contains processes.

Is there a way around this?

[nakengelhardt]

It looks like you haven't run any of the synthesis flow before your command. abc only works on gate-level netlists, so make sure to run the rest of the flow first, e.g. synth -noabc -top <top_module_name>. Also remember that abc only handles the combinatorial parts of the circuit and you will need to run dfflibmap to map flip-flops.