Regex-based pattern to consider certain modules as blackboxes

[pidgeon777]

In my input verilog file I have a certain amount of modules, e.g.:

module xxx
(
...
)

module yyy
(
...
)

Let suppose that I want to define all modules starting with yyy as blackboxes. Actually I have to manually do this:

(* blackbox *)
module yyy
(
...
)

Is there any yosys command/option, or any way in general, to automatically consider as blackboxes the modules whose name is identified by a pattern?

[nakengelhardt]

The blackbox command, like most yosys commands, takes a selection argument, and those support wildcards. It's not full regex but it can do what you need: blackbox t:\yyy* should do it (plus minus the \, I haven't tested). You can put this command right after read_verilog and before hierarchy (or any synth_xxx command you are using that includes hierarchy).
Documentation for blackbox
Documentation for selection mini-language