internal cells

[jalcim]

whats difference betwin ($DLATCH_P $DLATCH_N) ? (posedge negedge ?)

In the documentation, we doesn't have a section who list all internal cell.
internal cells of yosys aren't in a liberty file but only in the C++ ?
its possible to desactivate the internal cells of yosys ?

[nakengelhardt]

There is a section listing all the internal cells here: https://yosyshq.readthedocs.io/projects/yosys/en/latest/CHAPTER_CellLib.html#gates

They are also documented within yosys by the help command:

yosys> help $_DLATCH_P_

    $_DLATCH_P_ (E, D, Q)

A positive enable D-type latch.

Truth table:    E D | Q
               -----+---
                1 d | d
                - - | q

Run 'help $_DLATCH_P_+' to display the Verilog model for this cell type.


yosys> help $_DLATCH_P_+

module \$_DLATCH_P_ (E, D, Q);
    input E, D;
    output reg Q;
    always @* begin
        if (E == 1)
            Q <= D;
    end
endmodule

yosys> help $_DLATCH_N_

    $_DLATCH_N_ (E, D, Q)

A negative enable D-type latch.

Truth table:    E D | Q
               -----+---
                0 d | d
                - - | q

Run 'help $_DLATCH_N_+' to display the Verilog model for this cell type.


yosys> help $_DLATCH_N_+

module \$_DLATCH_N_ (E, D, Q);
    input E, D;
    output reg Q;
    always @* begin
        if (E == 0)
            Q <= D;
    end
endmodule