Assign statement in netlist

[lokki11199]

I am mapping the PWM module to this cell library: [(https://github.com/mflowgen/freepdk-45nm)]
Code of the PWM module:
module PWM(clk, reset, LED);
input clk, reset;
output LED;

reg [26:0] cnt;
reg [3:0] pwm_cnt;

always @(posedge clk)
if (reset)
cnt <= 27'd0;
else
cnt<=cnt+27'd1;

wire [3:0] pwm_inp = cnt[26] ? ~cnt[25:22]: cnt[25:22];

always @(posedge clk)
if (reset)
pwm_cnt <= 4'd0;
else
pwm_cnt <= pwm_cnt + 4'd1;

assign LED = (pwm_cnt<pwm_inp);

endmodule

Yosys script:
read_verilog PWM.v

proc

opt

techmap

opt -full

dfflibmap -liberty stdcells.lib

opt

abc -liberty stdcells.lib

opt_clean -purge

write_verilog PWM_synth.v

In the netlist I get an "assign" expression. Since I am further using OpenSTA for STA, which requires a simple rtl verilog file without "assign", I need to replace the "assign" with buffers, how do I do this?

[nakengelhardt]

Usually opt_clean -purge should get rid of these... but maybe the insbuf command may help: https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/insbuf.html