Erratic ABC result

[astrollo]

I have tried to synthesize a simple 4 bit mux:

read_verilog -sv << EOF
module mux4 #(parameter N=2)
(input logic [N-1:0] a3, a2, a1, a0,
input logic [1:0] s,
output logic [N-1:0] y);
always_comb
case (s)
2'b00 : y = a0;
2'b01 : y = a1;
2'b10 : y = a2;
default : y = a3;
endcase
endmodule
EOF

prep
pmuxtree
simplemap
abc
show

The results are quite different, depending on the size of the operands. For N=1 the synthesis includes 3 MUXex, as expected.
ABC RESULTS: MUX cells: 3
ABC RESULTS: internal signals: 18
ABC RESULTS: input signals: 6
ABC RESULTS: output signals: 1

For N=2 no MUXes are inferred, but simple AND/NOR/NAND gates.
ABC RESULTS: ANDNOT cells: 2
ABC RESULTS: NOR cells: 1
ABC RESULTS: AND cells: 5
ABC RESULTS: NAND cells: 10
ABC RESULTS: internal signals: 20
ABC RESULTS: input signals: 10
ABC RESULTS: output signals: 2

Similar behaviour for larger N values. Is it possible to obtain consistent results (inferring MUXes) for every N value? Thanks.

[nakengelhardt]

This is chosen by ABC. I don't think there's any way to control what it does. We can't even manage to get consistent results for identical designs that only differ in variable names!