How to use customized cells to generate blif (or other format) files

[YiKangOY]

I have modified the simlib.v file in /usr/local/share/yosys. I changed the "module $and" in line 126 to "module $andxxx" to test if I can make a cutomized cell. But I used write_blif command and I found that the and gate in the blif file still has the name "$and". I am wondering how can I change the cells that yosys used to generate a blif (or other formats) file.

Thanks!

[nakengelhardt]

The cells in the output are those in the netlist at the time the write is called (different sets of cells are allowed by different backends). It sounds like you want to map the cells to a a custom architecture or set of cells, there are various ways to do this depending on the use case. Can you describe a bit?

[YiKangOY]

I mainly use two backends, write_verilog and write_json because I want to represent a RTL code with some simple cells like and, or, etc.
I use the following code for conversion:
read_verilog xxx.v
hierarchy -top top
proc
memory_map
write_verilog (or write_json)
I found that the output verilog code will use the cells in https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simlib.v.
But I don't want it to use complex cells like $alu, $lcu, $macc (while cells like $mul, $div for basic operations are allowed).
How can I ensure that yosys will not use these complex cells, and how can I knwo what cells will yosys use?

Thank you!

[nakengelhardt]

Indeed, the flow you have posted is very minimal and just reads in the design and breaks down memory cells to FF cells. It will therefore leave the design in early elaboration stage, using the yosys internal representation described in chapter 5 of the manual (simlib.v is just where the behavior of these cells is specified for places that need it like simulation or whitebox optimization, but it is not where these cells are created from).

What you want to do is synthesis/technology mapping. Read chapter 9 of the manual and take a look at some of the synthesis passes for specific architectures, like synth_ice40 or synth_xilinx to see all the steps involved (help synth_ice40 will print a list of the passes called). The generic synth pass might be enough depending on what you want to do; it will map down to internal gate-level cells like $_AND_/$_OR_/$_NOT_ (and there is an option to ask it to map to luts of a specific size). You can use abc -g ... to map to a restricted set of gates as well.

[YiKangOY]

Sorry for didn't exlaborate my problem!

Actually I don't need synthesis and I only need to represent the verilog code by the cells in simlib.v and then re-write my verilog code for simulation.

I just want to ensure that only the basic cells in simlib.v (like $and, $add, $mul) for logical or arithmetic computations are used and the complex cells like $alu, $macc are not used.

For now I see only the basic cells are used, but I don't know what if I change my input verilog code.

Thanks!

[nakengelhardt]

For these cells specifically, the maccmap -unmap command will return them to $add, $mul etc.
More in general, you can use techmap -map +/techmap.v t:$<whatever> to map a cell type you do not want to appear, or you can create your own file similar to techmap.v with only the transformations you need.