Can I translate Structural Verilog to JSON with no optimizations?

[bkushigian]

I'm working on a project that generates Structural Verilog. I want to translate this to JSON so that I can run PnR. Yosys does a bunch of optimizations and for clarity I'd like to turn those off. Is there a way to run Yosys on a .sv file and have it translate it directly to JSON without doing anything fancy?

Example workflow

As an example of my desired workflow, suppose I run the following script:

read -sv module.sv
hierarchy -top example
proc; opt; techmap; opt
synth_ecp5
out.json
out.sv

This writes two files: out.json and out.sv.

What I'd like to do is run out.sv through yosys again and get something very similar to out.json, call it out2.json. In a perfect world the diff of out.json and out2.json would be empty but that's probably too much to hope for.

"Why do you want to do this?"

Great question!! I don't actually care about out.sv in the above example. In reality the .sv file would be generated by my tool (or by me messing around by hand), and I'd want to:

1. Test the stuff I'm outputting (if Yosys or PnR choke on my output file I know I've messed up)
2. Eventually use the designs I'm outputting on real boards!

[nakengelhardt]

Verilog is unfortunately the representation that is the furthest away from Yosys' internal representation (RTLIL), so there are more places for both the frontend and the backend to introduce differences. This would probably be much more likely to work if you were able to use RTLIL or JSON for the round-trip, but it seems that's not a possibility for your use case.

But generally, the shortest script to get json from a verilog file would be:

read_verilog out.sv
hierarchy -top example
proc
write_json out2.json

If your out.sv is actually structural, i.e. does not contain any always blocks, there is some chance that this will not be too far from the out.json of your first script. However, write_verilog does not produce structural code, it will actually create always blocks, e.g. for any FF types it recognizes, so this will work somewhat less well. The other major problem is that write_verilog will create _012_-style names for any elements with private names, and these now count as public names for the next round-trip. Maybe removing those with rename -hide n:_*_ could help somewhat?

[bkushigian]

This is super helpful, thank you @nakengelhardt! I've switched to outputting directly to JSON and now am using yosys -p "read_json XXX.json ; write_verilog YYY.sv" and life is good :D