how to change hierarchical separator

[gkamendje]

By default Yosys uses the dot . as the hierarchy separator. Is it possible to change it to something else like a forward slash / to match what I already have in my constraints file?

[nakengelhardt]

Can you give some context about where and how you want to use these paths? For example, . is the Verilog hierarchical separator and so is used in related contexts, but select uses / as separator.

[gkamendje]

Typical use case would be for the use of / as separator when writing SDC constraints. In the OpenRoad Flow Scripts flow for example, the design is flatten by default, hence it is quite difficult to write SDC constraints that would for instance create a generated clock on an internal pin or set a false path to/from an internal pin.

[whitequark]

In the hdlname attribute, post-flatten, the separator is unambiguously specified as (single space) which can be translated to any separator you want.

[gkamendje]

I am not sure I fully understand your answer. I am using YosYs in the OpenRoad Flow Scripts context. In my SDC constraints file, I would like for example to set a false path to the Test Enable pin of clock gating cells using a syntax such as: set_false_path -to [get_pins u1_inst/u2_inst/u3_inst/TE]. I have tried variants such as set_false_path -to [get_pins u1_inst?u2_inst?u3_inst?TE] , set_false_path -to [get_pins u1_inst.u2_inst.u3_inst/TE] or even set_false_path -to [get_pins u1_inst*u2_inst*u3_inst*TE] . I get errors stating that the pin could not be found. I don't know how to specify the path such that it could be found after flattening assuming that's possible at all.