Support for FIRRTL SeqMem primitives #3201
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hadirkhan10
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@azidar I am seeing some work being done in the yosys backend for FIRRTL.. does it support emitting SeqMem FIRRTL primitives for memories in verilog? I am not seeing any memory test here:
https://github.com/YosysHQ/yosys/blob/master/backends/firrtl/test.v
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