Input and Outputs of a Basic Wire Connection from Verilog-to-BLIF Output Are Reversed after 'opt_clean' pass

[mdko]

Note upfront: I'm not sure if this is actually a bug, so I've put what I expect and then actually get below. I'd appreciate any insight into what I'm misunderstanding or doing wrong if in fact it is not a bug. Thank you very much.

Steps to reproduce the issue

1. Unzip the attached files
2. Run yosys -s simple.ys
3. Observe the simple.blif and simple-back-from-yosys.v files based on the expected and actual behavior sections below.

Expected behavior

When I generate a .blif file from a Verilog file, I expect the directions of the connections to be the same as in the original Verilog file, in particular for output/input ports.

For example, given this very simple Verilog file:

module simple(outer);
   wire inner;
   output outer;

   assign outer = inner;
endmodule

after I run the following Yosys script:

read_verilog simple.v
hierarchy -check -top simple
proc
opt_expr; opt_merge; opt_muxtree; opt_reduce; opt_merge
opt_rmdff
dump
opt_clean
dump
opt_expr
write_blif -gates simple.blif
write_verilog simple-back-from-yosys.v

I would expect to get the following .blif file:

# Generated by Yosys 0.9+2406 (git sha1 2d573a0f, gcc 7.5.0-3ubuntu1~18.04 -fPIC -Os)

.model simple
.inputs
.outputs outer
.names $false
.names $true
1
.names $undef
.names inner outer
1 1
.end

Actual behavior

When I generate a .blif file from the above Verilog file using the above script, I actually get

# Generated by Yosys 0.9+2406 (git sha1 07eecff9, gcc 7.5.0-3ubuntu1~18.04 -fPIC -Os)

.model simple
.inputs
.outputs outer
.names $false
.names $true
1
.names $undef
.names outer inner
1 1
.end

In particular, the 3rd-to-last line .names outer inner is different.

More Information

I included the dump command before and after opt_clean in the above Yosys script to show where I think the possible problem (if this is determined to be a problem) is occurring.

The dump before opt_clean:

9. Executing OPT_RMDFF pass (remove dff with constant values).

autoidx 1

attribute \top 1
attribute \src "simple.v:1.1-6.10"
module \simple

  attribute \src "simple.v:3.11-3.16"
  wire output 1 \outer

  attribute \src "simple.v:2.9-2.14"
  wire \inner

  connect \outer \inner
end

the dump after opt_clean:

10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple..

autoidx 1

attribute \top 1
attribute \src "simple.v:1.1-6.10"
module \simple

  attribute \src "simple.v:2.9-2.14"
  wire \inner

  attribute \src "simple.v:3.11-3.16"
  wire output 1 \outer

  connect \inner \outer
end

(the difference is in the second-to-last lines, in the connect command).

Additionally, this is effecting the Verilog output; the following is what I get:

/* Generated by Yosys 0.9+2406 (git sha1 2d573a0f, gcc 7.5.0-3ubuntu1~18.04 -fPIC -Os) */

(* top =  1  *)
(* src = "simple.v:1.1-6.10" *)
module simple(outer);
  (* src = "simple.v:2.9-2.14" *)
  wire inner;
  (* src = "simple.v:3.11-3.16" *)
  output outer;
  assign inner = outer;
endmodule

(again, I would expect the second-to-last line to be assign outer = inner;)

A Less Trivial/Real-World Example

The above Verilog file was the smallest I could make that would exhibit what I think is a problem. However, I initially encountered this with a less trivial set of Verilog files found here.

To run them

1. Unzip the folder
2. Run yosys -s yosys_v2b.ys
3. Observe that in line 508 of the resulting bsg_fifo_1r1w_small_unhardened.blif, ready_o is the input to this net and ready_lo is the output, while in the original Verilog, ready_lo is in the input and ready_o is the output.

Note that this Yosys script has additional optimizations and passes and still has the purported error.

[daveshah1]

This is because opt_clean attempts to remove "alias names" - where more than one name applies to the same wire - out of any active paths to simplify the design, while still preserving the aliases as "dangling" connections.

Visualise this with the following example:

module top(input a, output q);
wire b = !a;
assign q = b;
endmodule

Before opt_clean, the assignment is in the cone of q:

After opt_clean, the assignment is optimised out, and an alias for b added to q instead, effectively reversing the assignment here too:

Hopefully, this clears up a bit what is going on and the rationale behind it. I would consider this intended behaviour of opt_clean/clean- which is an important part of any flow for multiple reasons - rather than a bug.