mismatch in pre- and post-synthesis simulations

[mehdimolum]

Hi,

I have a systemverilog design which simulates without problem using modelsim simulator (Intel's free version). I am able to synthesise the design using yosys without error (6 warnings of replacing memory with registers e.g., Warning: Replacing memory \row_weight with list of registers.). Nevertheless, the post-synthesis simulations are not what I expect (please see waveforms in this link ).

I have uploaded the code to EDA playground in this link

I am not sure if this a a bug or if I am missing something but would appreciate it if some one could help me with this

PS. This block populates the values of several tables (e.g., v_idx_list).