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fpga_interchange: Add initial site router test framework
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
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‎fpga_interchange/site_router_tests/CMakeLists.txt

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include(site_router_test.cmake)
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add_subdirectory(lut)

‎fpga_interchange/site_router_tests/common/run_script.tpl.py

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import sys
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print(
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"""
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import yaml
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def test_case(ctx):
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with open(""" + "\"" + sys.argv[1] + "\"" + """, 'r') as f:
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test_data = yaml.safe_load(f.read())
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if 'test_case' in test_data:
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ctx.pack()
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for test_step in test_data['test_case']:
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print(test_step)
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if "place" in test_step:
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for cell, bel in test_step["place"].items():
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print("Binding Bel {} to Cell {}".format(bel, cell))
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assert cell in ctx.cells, "Cell {} does not exist".format(cell)
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ctx.bindBel(bel, ctx.cells[cell], STRENGTH_WEAK)
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if "test" in test_step:
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print(test_step["test"])
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for bel, check in test_step["test"].items():
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print("Checking if location of bel {} is {}".format(bel, check))
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print("Test result: {}, isBelLocationValid: {}, expected: {}".format(ctx.isBelLocationValid(bel) == check, ctx.isBelLocationValid(bel), check))
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if "unplace" in test_step:
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print(test_step["unplace"])
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cell = test_step["unplace"]
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print("Unbinding Bel {}".format(cell))
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ctx.explain_bel_status(cell)
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ctx.unbindBel(cell)
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test_case(ctx)
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""")

‎fpga_interchange/site_router_tests/common/synth.tcl

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yosys -import
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read_verilog $::env(SOURCES)
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synth_xilinx -flatten -abc9 -nosrl -nocarry -nodsp
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# opt_expr -undriven makes sure all nets are driven, if only by the $undef
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# net.
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opt_expr -undriven
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opt_clean
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setundef -zero -params
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write_json $::env(OUT_JSON)

‎fpga_interchange/site_router_tests/lut/CMakeLists.txt

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add_site_router_test(
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name lut
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board arty35t
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test_script test.yaml
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sources lut.v
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)

‎fpga_interchange/site_router_tests/lut/lut.v

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module top(input [5:0] lut_1_in, input [4:0] lut_2_in, output lut_1_out, output lut_2_out);
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(* keep *)
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LUT6 #(.INIT(64'hFFFFFFFFFFFFFFFF)) lut_1 (
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.I0(lut_1_in[0]),
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.I1(lut_1_in[1]),
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.I2(lut_1_in[2]),
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.I3(lut_1_in[3]),
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.I4(lut_1_in[4]),
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.I5(lut_1_in[5]),
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.O(lut_1_out)
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);
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(* keep *)
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LUT5 #(.INIT(32'h0)) lut_2 (
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.I0(lut_1_in[0]),
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.I1(lut_2_in[1]),
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.I2(lut_2_in[2]),
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.I3(lut_2_in[3]),
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.I4(lut_2_in[4]),
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.O(lut_2_out)
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);
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endmodule

‎fpga_interchange/site_router_tests/lut/lut.xdc

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## arty-35t board
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set_property PACKAGE_PIN G13 [get_ports lut_1_in[0]]
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set_property PACKAGE_PIN B11 [get_ports lut_1_in[1]]
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set_property PACKAGE_PIN A11 [get_ports lut_1_in[2]]
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set_property PACKAGE_PIN D12 [get_ports lut_1_in[3]]
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set_property PACKAGE_PIN D13 [get_ports lut_1_in[4]]
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set_property PACKAGE_PIN B18 [get_ports lut_1_in[5]]
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set_property PACKAGE_PIN E15 [get_ports lut_2_in[0]]
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set_property PACKAGE_PIN E16 [get_ports lut_2_in[1]]
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set_property PACKAGE_PIN D15 [get_ports lut_2_in[2]]
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set_property PACKAGE_PIN C15 [get_ports lut_2_in[3]]
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set_property PACKAGE_PIN J17 [get_ports lut_2_in[4]]
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set_property PACKAGE_PIN H5 [get_ports lut_1_out]
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set_property PACKAGE_PIN J5 [get_ports lut_2_out]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[0]]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[1]]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[2]]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[3]]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[4]]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_1_in[5]]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_2_in[0]]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_2_in[1]]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_2_in[2]]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_2_in[3]]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_2_in[4]]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_1_out]
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set_property IOSTANDARD LVCMOS33 [get_ports lut_2_out]

‎fpga_interchange/site_router_tests/lut/test.yaml

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test_case:
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- place:
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# Place cell `lut_2` at BEL `SLICE_X1Y8.SLICEL/A6LUT`
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lut_1: SLICE_X1Y8.SLICEL/A6LUT
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- test:
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# Make sure this placement is accept
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SLICE_X1Y8.SLICEL/A6LUT: true
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- unplace:
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SLICE_X1Y8.SLICEL/A6LUT
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# - place:
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# lut_1: SLICE_X1Y8.SLICEL/B6LUT
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# - test:
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# # Make sure this placement is accept
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# SLICE_X1Y8.SLICEL/A6LUT: true
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# SLICE_X1Y8.SLICEL/B6LUT: true
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# - place:
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# lut_1: SLICE_X1Y8.SLICEL/A6LUT
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# lut_2: SLICE_X1Y8.SLICEL/A5LUT
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# - test:
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# # The site is now invalid because too many signals into the A6/A5LUT
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# SLICE_X1Y8.SLICEL/A6LUT: false
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# SLICE_X1Y8.SLICEL/A5LUT: false
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# - unplace:
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# - lut_2
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# - test:
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# # By removing lut_2, the site is valid again
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# SLICE_X1Y8.SLICEL/A6LUT: true
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# SLICE_X1Y8.SLICEL/A5LUT: true

‎fpga_interchange/site_router_tests/site_router_test.cmake

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function(add_site_router_test)
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# ~~~
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# add_site_router_test(
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# name <name>
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# board <board>
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# test_script <yaml>
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# sources <sources list>
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# [top <top name>]
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# )
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#
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# Generates targets to run desired site router tests.
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#
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# Arguments:
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# - name: base test name. The real test name will be <name>_<board>
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# - board: name of the board to be used in the test, e.g. arty35t
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# - test_script: YAML description of the test case
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# - sources: list of HDL sources
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# - top (optional): name of the top level module.
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# If not provided, "top" is assigned as top level module
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set(options)
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set(oneValueArgs name test_script board top)
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set(multiValueArgs sources)
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cmake_parse_arguments(
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add_site_router_test
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"${options}"
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"${oneValueArgs}"
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"${multiValueArgs}"
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${ARGN}
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)
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set(name ${add_site_router_test_name})
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set(test_script ${add_site_router_test_test_script})
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set(board ${add_site_router_test_board})
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set(top ${add_site_router_test_top})
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set(sources)
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get_property(device TARGET board-${board} PROPERTY DEVICE)
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get_property(package TARGET board-${board} PROPERTY PACKAGE)
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foreach(source ${add_site_router_test_sources})
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list(APPEND sources ${CMAKE_CURRENT_SOURCE_DIR}/${source})
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endforeach()
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if (NOT DEFINED top)
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# Setting default top value
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set(top "top")
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endif()
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set(common_dir ${CMAKE_CURRENT_SOURCE_DIR}/../common)
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# Synthesis
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set(synth_json ${CMAKE_CURRENT_BINARY_DIR}/${name}.json)
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add_custom_command(
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OUTPUT ${synth_json}
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COMMAND ${CMAKE_COMMAND} -E env
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SOURCES="${sources}"
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OUT_JSON=${synth_json}
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yosys -c ${common_dir}/synth.tcl
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DEPENDS ${sources}
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)
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add_custom_target(site_router_tests-${name}-json DEPENDS ${synth_json})
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# Logical Netlist
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get_property(device_target TARGET device-${device} PROPERTY DEVICE_TARGET)
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get_property(device_loc TARGET device-${device} PROPERTY DEVICE_LOC)
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set(netlist ${CMAKE_CURRENT_BINARY_DIR}/${name}.netlist)
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add_custom_command(
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OUTPUT ${netlist}
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COMMAND
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${PYTHON_EXECUTABLE} -mfpga_interchange.yosys_json
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--schema_dir ${INTERCHANGE_SCHEMA_PATH}
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--device ${device_loc}
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--top ${top}
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${synth_json}
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${netlist}
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DEPENDS
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${synth_json}
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${device_target}
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${device_loc}
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)
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add_custom_target(site_router_tests-${name}-netlist DEPENDS ${netlist})
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# Logical Netlist YAML
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set(netlist_yaml ${CMAKE_CURRENT_BINARY_DIR}/${name}.netlist.yaml)
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add_custom_command(
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OUTPUT ${netlist_yaml}
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COMMAND
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${PYTHON_EXECUTABLE} -mfpga_interchange.convert
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--schema_dir ${INTERCHANGE_SCHEMA_PATH}
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--schema logical
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--input_format capnp
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--output_format yaml
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${netlist}
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${netlist_yaml}
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DEPENDS
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${netlist}
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)
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add_custom_target(site_router_tests-${name}-netlist-yaml DEPENDS ${netlist_yaml})
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# Run script
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set(run_script ${CMAKE_CURRENT_BINARY_DIR}/${name}.py)
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add_custom_command(
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OUTPUT ${run_script}
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COMMAND
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${PYTHON_EXECUTABLE}
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${common_dir}/run_script.tpl.py
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${CMAKE_CURRENT_SOURCE_DIR}/${test_script} > ${run_script}
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DEPENDS
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${test_script}
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)
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add_custom_target(site_router_tests-${name}-run_script DEPENDS ${run_script})
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# Physical Netlist
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get_property(chipdb_bin_target TARGET device-${device} PROPERTY CHIPDB_BIN_TARGET)
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get_property(chipdb_bin_loc TARGET device-${device} PROPERTY CHIPDB_BIN_LOC)
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set(test_result ${CMAKE_CURRENT_BINARY_DIR}/${name}.test_result)
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set(xdc ${CMAKE_CURRENT_SOURCE_DIR}/${name}.xdc)
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add_custom_command(
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OUTPUT ${test_result}
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COMMAND
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nextpnr-fpga_interchange
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--run ${run_script}
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--no-route
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--chipdb ${chipdb_bin_loc}
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--xdc ${xdc}
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--netlist ${netlist}
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--package ${package} > ${test_result}
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DEPENDS
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nextpnr-fpga_interchange
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${netlist}
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${xdc}
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${chipdb_bin_target}
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${chipdb_bin_loc}
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${run_script}
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)
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add_custom_target(site_router_tests-${name}-test DEPENDS ${test_result})
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endfunction()

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