arch: multiple delay slot support, suppress spurious mips warning

Author: rssor

arch/mips/arch_mips.cpp

@@ -301,7 +301,7 @@ class MipsArchitecture: public Architecture
 			if (instr.operands[0].immediate != addr + 8)
 				result.AddBranch(CallDestination, instr.operands[0].immediate, nullptr, hasBranchDelay);
 			else
-				result.branchDelay = 1; // We have a "get pc" mnemonic; do nothing
+				result.delaySlots = 1; // We have a "get pc" mnemonic; do nothing
 			break;
 
 		case MIPS_JAL:
@@ -311,7 +311,7 @@ class MipsArchitecture: public Architecture
 		//Jmp to register register value is unknown
 		case MIPS_JALR:
 		case MIPS_JALR_HB:
-			result.branchDelay = 1;
+			result.delaySlots = 1;
 			break;
 
 		case MIPS_BGEZAL:

arch/riscv/src/lib.rs

@@ -687,7 +687,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
             _ => return None,
         };
 
-        let mut res = InstructionInfo::new(inst_len, false);
+        let mut res = InstructionInfo::new(inst_len, 0);
 
         match op {
             Op::Jal(ref j) => {

architecture.cpp

@@ -34,15 +34,15 @@ InstructionInfo::InstructionInfo()
 	length = 0;
 	archTransitionByTargetAddr = false;
 	branchCount = 0;
-	branchDelay = false;
+	delaySlots = 0;
 }
 
 
-void InstructionInfo::AddBranch(BNBranchType type, uint64_t target, Architecture* arch, bool hasDelaySlot)
+void InstructionInfo::AddBranch(BNBranchType type, uint64_t target, Architecture* arch, uint8_t delaySlot)
 {
 	if (branchCount >= BN_MAX_INSTRUCTION_BRANCHES)
 		return;
-	branchDelay = hasDelaySlot;
+	delaySlots = delaySlot;
 	branchType[branchCount] = type;
 	branchTarget[branchCount] = target;
 	branchArch[branchCount++] = arch ? arch->GetObject() : nullptr;
@@ -242,6 +242,7 @@ bool Architecture::GetInstructionInfoCallback(
 	CallbackRef<Architecture> arch(ctxt);
 
 	InstructionInfo info;
+	info.delaySlots = result->delaySlots;
 	bool ok = arch->GetInstructionInfo(data, addr, maxLen, info);
 	*result = info;
 	return ok;

binaryninjaapi.h

@@ -7569,7 +7569,7 @@ namespace BinaryNinja {
 	struct InstructionInfo : public BNInstructionInfo
 	{
 		InstructionInfo();
-		void AddBranch(BNBranchType type, uint64_t target = 0, Architecture* arch = nullptr, bool hasDelaySlot = false);
+		void AddBranch(BNBranchType type, uint64_t target = 0, Architecture* arch = nullptr, uint8_t delaySlots = 0);
 	};
 
 	struct NameAndType

binaryninjacore.h

@@ -37,14 +37,14 @@
 // Current ABI version for linking to the core. This is incremented any time
 // there are changes to the API that affect linking, including new functions,
 // new types, or modifications to existing functions or types.
-#define BN_CURRENT_CORE_ABI_VERSION 63
+#define BN_CURRENT_CORE_ABI_VERSION 64
 
 // Minimum ABI version that is supported for loading of plugins. Plugins that
 // are linked to an ABI version less than this will not be able to load and
 // will require rebuilding. The minimum version is increased when there are
 // incompatible changes that break binary compatibility, such as changes to
 // existing types or functions.
-#define BN_MINIMUM_CORE_ABI_VERSION 62
+#define BN_MINIMUM_CORE_ABI_VERSION 64
 
 #ifdef __GNUC__
 	#ifdef BINARYNINJACORE_LIBRARY
@@ -1685,7 +1685,7 @@ extern "C"
 		size_t length;
 		size_t branchCount;
 		bool archTransitionByTargetAddr;
-		bool branchDelay;
+		uint8_t delaySlots;
 		BNBranchType branchType[BN_MAX_INSTRUCTION_BRANCHES];
 		uint64_t branchTarget[BN_MAX_INSTRUCTION_BRANCHES];
 		BNArchitecture* branchArch[BN_MAX_INSTRUCTION_BRANCHES];  // If null, same architecture as instruction

python/architecture.py

@@ -131,7 +131,7 @@ def __repr__(self):
 class InstructionInfo:
 	length: int = 0
 	arch_transition_by_target_addr: bool = False
-	branch_delay: bool = False
+	branch_delay: int = 0
 	branches: List[InstructionBranch] = field(default_factory=list)
 
 	def add_branch(self, branch_type: BranchType, target: int = 0, arch: Optional['Architecture'] = None) -> None:
@@ -648,7 +648,7 @@ def _get_instruction_info(self, ctxt, data, addr, max_len, result):
 				return False
 			result[0].length = info.length
 			result[0].archTransitionByTargetAddr = info.arch_transition_by_target_addr
-			result[0].branchDelay = info.branch_delay
+			result[0].delaySlots = info.branch_delay
 			result[0].branchCount = len(info.branches)
 			for i in range(0, len(info.branches)):
 				if isinstance(info.branches[i].type, str):
@@ -2346,7 +2346,7 @@ def get_instruction_info(self, data: bytes, addr: int) -> Optional[InstructionIn
 		result = InstructionInfo()
 		result.length = info.length
 		result.arch_transition_by_target_addr = info.archTransitionByTargetAddr
-		result.branch_delay = info.branchDelay
+		result.branch_delay = info.delaySlots
 		for i in range(0, info.branchCount):
 			target = info.branchTarget[i]
 			if info.branchArch[i]:

rust/src/architecture.rs

@@ -97,11 +97,11 @@ impl<'a> Iterator for BranchIter<'a> {
 #[repr(C)]
 pub struct InstructionInfo(BNInstructionInfo);
 impl InstructionInfo {
-    pub fn new(len: usize, branch_delay: bool) -> Self {
+    pub fn new(len: usize, delay_slots: u8) -> Self {
         InstructionInfo(BNInstructionInfo {
             length: len,
             archTransitionByTargetAddr: false,
-            branchDelay: branch_delay,
+            delaySlots: delay_slots,
             branchCount: 0usize,
             branchType: [BranchType::UnresolvedBranch; 3],
             branchTarget: [0u64; 3],
@@ -121,8 +121,8 @@ impl InstructionInfo {
         self.0.branchCount
     }
 
-    pub fn branch_delay(&self) -> bool {
-        self.0.branchDelay
+    pub fn delay_slots(&self) -> u8 {
+        self.0.delaySlots
     }
 
     pub fn branches(&self) -> BranchIter {