Help debugging -connect_to_pads

[stockstephanie]

Hi all,
I've recently updated a PDK to its latest version and have had some issues with the PDN not connecting to the north and south rows of pads. In the previous version, the pads are routed fine.
Latest pad ring connections:

Previous pad ring connections:

The only differences that I can think of that are relevant that I have found are that the top two layers are now what are used to connect to the pad cells, whereas metal 4 and 5 were used in the previous version. Any help or advice would be greatly appreciated!
PDN.tcl

add_global_connection -net VDD -pin_pattern {^VDDL$}
add_global_connection -net VSS -pin_pattern {^VSS$} -ground

global_connect

set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}

define_pdn_grid -name {Core} -voltage_domains {CORE}
add_pdn_ring -grid "Core" -layers {M6 M7} -widths 8.00 -spacings 2.00 -pad_offsets {8 8} -connect_to_pads

add_pdn_stripe -layer {M2} -pitch {7.68} -offset {0} -followpins
add_pdn_stripe -layer {M6} -width {2.00} -pitch {50.00} -offset {7.00} -extend_to_core_ring
add_pdn_stripe -layer {M7} -width {2.00} -pitch {50.00} -offset {7.00} -extend_to_core_ring

add_pdn_connect -layers {M2 M6}
add_pdn_connect -layers {M6 M7} 
pdngen

[maliberty]

@gadfort suggestions?

[stockstephanie]

That's my bad. MTK1 and MRF1 are the top two layers (M6/M7) that I had renamed in the rest of the script to make a little more sense in the context. I updated the code block.

[gadfort]

@stockstephanie I still think you need some add_pdn_connect between the layers the IO pins are on and M6 and M7 (it looks like there are pins on M6 which is why the left and right are connecting to M7), but you will need something for M5 -> M6 (assuming m5 has pins)

[stockstephanie]

@gadfort M5 does not have pins in the version of the pad cells I am using. It did in the previous version of the pad cells. There are M6 and M7 pins for the PDN to access now. I have also ran into an issue where if I use -followpins with the M2 stripe and then use add_pdn_connection to M6 where it says that there is no more room to access channels; I'm not sure if these two issues are related.
It's probably one small difference that I have missed when updating the platform or design files, I'm just not entirely sure what could be causing such a big difference between the two setups. I spent all day yesterday trying to debug it.

[gadfort]

@stockstephanie M2 should not attempt to connect to M6 (since they have the same direction).
As for the pad cells, it's difficult to further debug this without access to the design, it looks like PDN is trying to place the straps, but is failing to for some reason.

[stockstephanie]

@gadfort I continued working on this some and I think I understand the problem a bit better. All of the pad connections are made to the ring if the ports for VSS/VDD are on M4 and M5. I think the issues come in where the M6/M7 connections between the routes and straps happen because there is interference with the pad connections since they are on the same layers. Unfortunately, I can't keep those connections on M4 and M5 though due to DRC rule violations that would occur from the routes being that wide. Is there a way to forgo the use of a pad ring and only use stripes while still connecting them to the pads?

[stockstephanie]

@gadfort I did change the M2 connection to M7 but with the -followpins flag it is still failing. I'm not able to share much information on the PDK unfortunately, I was hoping there was someone who had randomly come across something similar after setting up a new platform.