ihp-sg32g2: Pin Enclosure?

[dnltz]

I'm working on a hierarchy flow with the IHP SG32G2 PDK. Blocks have MetalX.pin shapes at the boundary but apparently they need to be fully enclosed by MetalX.drawing. See page 70 of the Layout Rules Rev 0.4:

Circuit designers should use only drawing purpose 0 (data types) for layouts. Only exception is pin purpose
2 for symbolic pins. Data type 2 (purpose pin) is used for symbolic connectivity information. Pin areas must
be fully covered by drawing. These rules are tested because pin areas are not used for mask generation
and a potential issue due to false postive LVS matchs.

This is a screenshot from my layout, the pin shape is generating DRC violations.

So, are there any flags/commands/... to add enclose these pins with drawing?

[maliberty]

It would be easier if you formulated this in OR terms instead of GDS. OR doesn't directly generate GDS. I can't tell from the image/description what the problem is.

[dnltz]

@maliberty my block has a pin (selected on the screenshot). I need the signal shape to fully cover the pin shape, but right now they only touch at the connection point.

Does that make more sense? Always forget this is not GDS :)

[maliberty]

This is a very weird rule. There is no such option to cover pins in the router as it isn't normally required. I suggest you map your DEF pins to drawing in the gds.

"pin areas are not used for mask generation" sounds like a recipe for disaster...

[dnltz]

@maliberty I opened an issue in the Open PDK to discuss that. Updating the .map file actually fixes this issue but I'm not aware of any consequences.

and yes, sounds like a bad idea to skip shapes during mask generation.

Thank you for your input :)