Workaround for using module as a blackbox?

[yswntht]

Hi @maliberty ,

I was trying to add a different configuration of Rocket CPU generated using chipyard to OpenROAD-flow-scripts/flow/designs (similar to tinyRocket example provided). When I run make synth, I see following error: ERROR: Missing cost information on instanced blackbox data_arrays_0_ext. (I must say I just defined the memory module as blackbox and have not added a .lib file using sram generator)

I see few closed issues (e.g. #175 and #2054) discussing this that .lib files are be added for all macros. Is there a work around for this where I can skip adding .lib files to all the memory modules? (at the moment I'm just focused on synthesis).

[maliberty]

@povik any thoughts as this isn't really an ORFS issue afaik.

[yswntht]

Thank you. I tested both the methods and both are working.

[yswntht]

@povik ,

Applying the second method (* gate_cost_equivalent=N *), I tried to synthesize (Large BoomTile) on our local server.
After running for a while, the run got killed due to not sufficient memory (copied the log below at the point of failure). I'm not entirely sure if this is a memory size issue. For large designs (e.g MegaBoom) what is the typical memory usage? Any thoughts on what could be the issue here? (flow I'm using: (1) chipyard to system verilog, (2) use bsg_sv2v to convert to verilog (3) apply (* blackbox, gate_cost_equivalent=1240 *) on all memory modules (4) Finally make synth)

6.9.323. Executing OPT_EXPR pass (perform const folding).
6.9.324. Finished OPT passes. (There is nothing left to do.)
6.10. Executing WREDUCE pass (reducing word size of cells).
6.11. Executing PEEPOPT pass (run peephole optimizers).
6.12. Executing OPT_CLEAN pass (remove unused cells and wires).
6.13. Executing ALUMACC pass (create $alu and $macc cells).
6.14. Executing SHARE pass (SAT-based resource sharing).
Command terminated by signal 9
Elapsed time: 4:28:47[h:]min:sec. CPU time: user 15758.48 sys 298.18 (99%). Peak memory: 776388832KB.
make[1]: *** [Makefile:470: do-yosys] Error 137
make: *** [Makefile:482: results/nangate45/largeboom/base/1_1_yosys.v] Error 2

Any pointers are helpful.

Thanks.

[povik]

@yswntht I think you are running into an issue with the share pass where it can exhaust memory on some inputs. There's ongoing work to fix this: YosysHQ/yosys#4904 As a workaround you can set the flow variable SYNTH_ARGS="-flatten -noshare" (-flatten is in this variable by default, this adds -noshare)

[widlarizer]

Currently, the yosys share pass unfortunately "just does that sometimes" for two separate reasons. While the share pass is written using a potentially computationally intensive SAT solver approach, it's likely you've run into an unfortunate case that would be mitigated by YosysHQ/yosys#4904. It would be best if you could check if that yosys PR helps or provided the files with reproduction steps. You can also see the issues linked in that PR to learn more about the potential future direction we might take the share pass if you're interested

As a workaround you should try adding -noshare to ORFS variable SYNTH_ARGS to avoid running the share pass

[yswntht]

Thank you @povik and @widlarizer . Adding -noshare to SYNTH_ARGS, I can now successfully synthesize the design.