Output Verilog netlist without power / ground

[AkaBlur]

Hi all,
I'm currently working on an implementation of ORFS for some of my companies PDKs. I've also got it to work quite well. But now I'm facing an issue.
For verification I wanted to do LVS with Cadence PVS with the DEF I generated. When reading in the DEF into Virtuoso I noticed that the supply net connections for all of my cells are missing. The PDN though was configured and routed correctly. I had a look into the DEF and noticed that there are no SPECIALNET entries for my SC instances.
Is that correct?

I also tried one of the integrated example designs: sky130hd/gcd. There I also didn't found any net definitions inside the SPECIALNETS entry inside the DEF.

For clarification, inside a reference design flow we use this would be an example that is written to the DEF:

SPECIALNETS 5 ;
...
- vdd_A
...
( core/pipe_mu2_mul_18_52_g4967 vddi )

This is an instance of an OR gate which has an entry inside SPECIALNETS were it is clearly connected to vddi (one of the power rails).

Is there an option where ORFS can output this data as well in the DEF?

Best regards.

[maliberty]

In gcd you can see the connections are there:

SPECIALNETS 2 ;
- VDD ( * VDD ) + USE POWER

With no test case I don't know what the issue is in your case. Any such connections are in the DEF, there is no separate option. It would be better to file an issue with a test case.

[AkaBlur]

Sorry about the confusion, I messed up the LVS on my side. I think the DEF should be fine as you said.

The issue wasn't the layout, more so the netlist I was using:
In the results from flow-scripts I found (in my case) netlists from the synthesis in step 1 and 6 but none of them contain instances with power and ground connections.
I also checked the testcase from ORFS but also I didn't found any netlist with power/ground included.

Can ORFS output a Verilog netlist with power/ground?
Or is this something I should investigate within Yosys?

[maliberty]

write_verilog -include_pwr_gnd <filename> should do it

[rovinski]

Also, you should look at writing out the CDL rather than the verilog for LVS. See write_cdl

[AkaBlur]

Thanks for the help with the Verilog :D Works as expected

Also @rovinski, good to know that OpenROAD also has the option to write a CDL.