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#define CP_BSS (1)
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#define CP_ALLOCATIONS (1)
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- #define GDB_LOG_CP (1 )
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+ #define GDB_LOG_CP (0 )
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/* Debug options */
@@ -145,6 +145,44 @@ digitalio_digitalinout_obj_t rst_pin_nv;
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digitalio_digitalinout_obj_t pfail_pin_nv ;
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+ /**
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+ * Benchmark
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+ */
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+
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+ digitalio_digitalinout_obj_t cpbench_checkpoint_pin ;
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+ digitalio_digitalinout_obj_t cpbench_restore_pin ;
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+ #define CPBENCH_CHECKPOINT_PINDEF (&pin_PA08) // D4
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+ #define CPBENCH_RESTORE_PINDEF (&pin_PA15) // D5
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+
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+ static inline void cpbench_init (void ) {
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+ #if CHECKPOINT_BENCHMARK
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+ cpbench_checkpoint_pin .base .type = & digitalio_digitalinout_type ;
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+ common_hal_digitalio_digitalinout_construct (& cpbench_checkpoint_pin , CPBENCH_CHECKPOINT_PINDEF );
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+ common_hal_digitalio_digitalinout_switch_to_output (& cpbench_checkpoint_pin , true, DRIVE_MODE_PUSH_PULL );
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+ common_hal_digitalio_digitalinout_never_reset (& cpbench_checkpoint_pin );
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+ common_hal_digitalio_digitalinout_set_value (& cpbench_checkpoint_pin , false);
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+
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+ cpbench_restore_pin .base .type = & digitalio_digitalinout_type ;
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+ common_hal_digitalio_digitalinout_construct (& cpbench_restore_pin , CPBENCH_RESTORE_PINDEF );
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+ common_hal_digitalio_digitalinout_switch_to_output (& cpbench_restore_pin , true, DRIVE_MODE_PUSH_PULL );
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+ common_hal_digitalio_digitalinout_never_reset (& cpbench_restore_pin );
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+ common_hal_digitalio_digitalinout_set_value (& cpbench_restore_pin , false);
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+ #endif
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+ }
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+
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+ static inline void cpbench_checkpoint_pin_set_value (bool value ) {
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+ #if CHECKPOINT_BENCHMARK
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+ common_hal_digitalio_digitalinout_set_value (& cpbench_checkpoint_pin , value );
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+ #endif
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+ }
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+
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+ static inline void cpbench_restore_pin_set_value (bool value ) {
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+ #if CHECKPOINT_BENCHMARK
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+ common_hal_digitalio_digitalinout_set_value (& cpbench_restore_pin , value );
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+ #endif
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+ }
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+
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+
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void nvm_wait_process (void ) {
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// Wait untill the NVM signals it's ready
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while (common_hal_digitalio_digitalinout_get_value (& wr_pin_nv ) == false) {
@@ -188,6 +226,9 @@ void nvm_comm_init(void) {
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common_hal_digitalio_digitalinout_construct (& pfail_pin_nv , & pin_PA20 );
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common_hal_digitalio_digitalinout_switch_to_input (& pfail_pin_nv , PULL_NONE );
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common_hal_digitalio_digitalinout_never_reset (& pfail_pin_nv );
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+
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+ /* Benchmark pins */
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+ cpbench_init ();
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}
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void nvm_reset (void ) {
@@ -427,6 +468,8 @@ __attribute__((noinline))
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static int pyrestore_process (void ) {
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segment_size_t addr_start , addr_end , size ;
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+ cpbench_restore_pin_set_value (true);
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+
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nvm_write_byte (CPCMND_REQUEST_RESTORE );
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bool restore_registers_pending = false;
@@ -561,6 +604,7 @@ void pyrestore(void) {
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uint32_t checkpoint_skipped = 0 ; // skip count
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uint32_t checkpoint_performed = 0 ; // checkpoint count
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+ uint32_t checkpoint_restore_performed = 0 ; // restore count
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static inline void checkpoint_schedule_callback (void );
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@@ -597,6 +641,8 @@ int checkpoint(void)
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return 0 ;
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}
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+ cpbench_checkpoint_pin_set_value (true);
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+
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nvm_write_byte (CPCMND_REQUEST_CHECKPOINT );
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resp = nvm_read_byte ();
@@ -618,6 +664,8 @@ int checkpoint(void)
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if (checkpoint_restored () == 0 ) {
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/* Normal operation */
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nvm_write_byte (CPCMND_CONTINUE );
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+ } else {
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+ ++ checkpoint_restore_performed ;
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}
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/* remove the pending status */
@@ -628,6 +676,14 @@ int checkpoint(void)
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checkpoint_performed ++ ;
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+ #if CHECKPOINT_BENCHMARK
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+ if (checkpoint_restored () == 0 ) {
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+ cpbench_checkpoint_pin_set_value (false);
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+ } else {
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+ cpbench_restore_pin_set_value (false);
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+ }
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+ #endif
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+
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return checkpoint_restored ();
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}
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#endif /* CP_CHECKPOINT_DISABLE */
@@ -696,13 +752,13 @@ static void checkpoint_schedule_update_time(const uint64_t period_ms) {
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static void checkpoint_schedule_update_trigger (void ) {
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// If the threshold voltage is reached PFAIL is high
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- if (common_hal_digitalio_digitalinout_get_value (& pfail_pin_nv ) == true ) {
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+ if (common_hal_digitalio_digitalinout_get_value (& pfail_pin_nv ) == false ) {
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checkpoint_schedule_update_time (checkpoint_cfg .cps_period_ms );
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}
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}
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static void checkpoint_schedule_update_hybrid (void ) {
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- if (common_hal_digitalio_digitalinout_get_value (& pfail_pin_nv ) == true ) {
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+ if (common_hal_digitalio_digitalinout_get_value (& pfail_pin_nv ) == false ) {
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checkpoint_schedule_update_time (checkpoint_cfg .cps_period_ms );
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} else {
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checkpoint_schedule_update_time (checkpoint_cfg .cps_hybrid_period_ms );
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