Best Practice for Modeling W1S and W1C Access to Same Bits

[vgaliCelero]

Hi team,

I'm trying to model a hardware register where software can:

Set bit using Write-1-to-Set (W1S)

Clear bit using Write-1-to-Clear (W1C)

Read back the current value of the bit

All of these operations should target the same hardware bit.

Appreciate any clarification or best practices for this use case.

Thanks!
Vasu

[amykyta3]

It is not clear to me how this is possible. If software writes 1 to a bit, what would the effect be if the same bit would clear and set if written with a 1?
Having both behaviors would be contradictory.

[vgaliCelero]

Hi.

Here is the detailed explanation.

Register name           Access type             Action
clock_enable_set        w1s                     Write 1 to set clock_enable
clock_enable_clr        w1c                     Write 1 to clear clock_enable

Both registers map to the same underlying hardware field clock_enable, but from a software point of view, they are separate registers with distinct access semantics.

[amykyta3]

Ah i see what you mean. This is possible by creating separate trigger bits using a combination of the singlepulse, hwset, and hwclr properties.

See below:

reg {
    field {
        // Implements the actual storage element for the clock-enable field
        sw = rw; // Software can write this to 1 or 0 directly if desired
        hw = r; // provide state of this bit to hardware
    } clock_enable = 0;
} clock_ctrl;


reg {
    // Define a generic trigger bit
    field trigger_bit {
        sw = w; // write-only
        hw = na; // hwif does not need access
        singlepulse; // If software writes this to 1, clears back to 0 automatically on the next clock cycle.
    };

    // Instantiate two triggers - one to set and one to clear the clock enable
    trigger_bit clock_enable_set = 0;
    trigger_bit clock_enable_clr = 0;
} clock_set_clr_ctrl;

// Set and clear the clock_enable using the value of the trigger bits
clock_ctrl.clock_enable->hwset = clock_set_clr_ctrl.clock_enable_set;
clock_ctrl.clock_enable->hwclr = clock_set_clr_ctrl.clock_enable_clr;

[vgaliCelero]

Thank you so much. I'll give it a try!