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deathaxedeathaxe
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Merge branch 'develop'
2 parents 8410a14 + d58fc82 commit 18b405f

26 files changed

+64
-27
lines changed

‎.github/workflows/ci.yaml

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with:
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python-version-file: '.python-version'
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- name: Install dependencies
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run: python -m pip install -U -r requirements-dev.txt
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- name: Install Black
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run: python -m pip install -U black
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- name: Check formatting
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run: python -m black --check .

‎icons/icons.json

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}
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]
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},
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"file_type_systemverilog": {
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"color": "blue",
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"syntaxes": [
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{
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"extensions": [
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"sv",
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"svh",
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"vh"
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],
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"name": "Plain Text (SystemVerilog)",
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"scope": "source.systemverilog"
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}
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]
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},
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"file_type_taskfile": {
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"aliases": [
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{
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"syntaxes": [
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{
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"extensions": [
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"tailwind.css"
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"tailwind.css",
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"tailwind.pcss",
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"tailwind.postcss"
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],
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"name": "Plain Text (Tailwind CSS)",
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"scope": "source.css.tailwind"
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"scope": "source.css.tailwind, source.postcss.tailwind"
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}
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]
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},
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"syntaxes": [
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{
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"extensions": [
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"v",
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"vlang"
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],
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"name": "Plain Text (V)",
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],
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"color": "sky"
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},
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"file_type_verilog": {
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"color": "blue",
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"syntaxes": [
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{
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"extensions": [
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"v"
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],
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"name": "Plain Text (Verilog)",
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"scope": "source.verilog"
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}
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]
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},
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"file_type_vhdl": {
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"color": "blue",
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"syntaxes": [
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],
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"name": "Plain Text (VHDL)",
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"scope": "source.vhdl"
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},
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{
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"extensions": [
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"sv",
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"v",
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"svh",
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"vh"
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],
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"name": "Plain Text (SystemVerilog)",
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"scope": "source.systemverilog"
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},
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{
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"extensions": [
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"v",
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"V"
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],
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"name": "Plain Text (Verilog)",
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"scope": "source.verilog"
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}
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]
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},

‎icons/multi/file_type_systemverilog.png

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‎icons/multi/file_type_systemverilog@2x.png

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‎icons/multi/file_type_systemverilog@3x.png

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‎icons/multi/file_type_verilog.png

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‎icons/multi/file_type_verilog@2x.png

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‎icons/multi/file_type_verilog@3x.png

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‎icons/single/file_type_systemverilog.png

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‎icons/single/file_type_systemverilog@2x.png

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‎icons/single/file_type_systemverilog@3x.png

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‎icons/single/file_type_verilog.png

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‎icons/single/file_type_verilog@2x.png

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‎icons/single/file_type_verilog@3x.png

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‎icons/svg/file_type_systemverilog.svg

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‎icons/svg/file_type_verilog.svg

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‎preferences/file_type_systemverilog.tmPreferences

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<?xml version="1.0" encoding="UTF-8"?>
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<plist version="1.0">
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<dict>
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<key>scope</key>
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<string>source.systemverilog</string>
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<key>settings</key>
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<dict>
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<key>icon</key>
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<string>file_type_systemverilog</string>
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</dict>
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</dict>
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</plist>

‎preferences/file_type_tailwind.tmPreferences

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<plist version="1.0">
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<dict>
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<key>scope</key>
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<string>source.css.tailwind, source.js.tailwind, source.ts.tailwind</string>
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<string>source.css.tailwind, source.js.tailwind, source.postcss.tailwind, source.ts.tailwind</string>
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<key>settings</key>
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<dict>
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<key>icon</key>

‎preferences/file_type_verilog.tmPreferences

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<?xml version="1.0" encoding="UTF-8"?>
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<plist version="1.0">
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<dict>
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<key>scope</key>
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<string>source.verilog</string>
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<key>settings</key>
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<dict>
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<key>icon</key>
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<string>file_type_verilog</string>
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</dict>
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</dict>
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</plist>

‎preferences/file_type_vhdl.tmPreferences

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<plist version="1.0">
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<dict>
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<key>scope</key>
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<string>source.systemverilog, source.verilog, source.vhdl</string>
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<string>source.vhdl</string>
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<key>settings</key>
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<dict>
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<key>icon</key>

‎requirements-dev.txt

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pip
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# Build
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cairosvg >= 2.7.0
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pypng >= 0.20220715.0

‎tests/file_type_v.v renamed to ‎tests/file_type_systemverilog.sv

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‎tests/file_type_vhdl.sv renamed to ‎tests/file_type_systemverilog.svh

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‎tests/file_type_vhdl.svh renamed to ‎tests/file_type_systemverilog.vh

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‎tests/file_type_vhdl.v renamed to ‎tests/file_type_verilog.v

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‎tests/file_type_vhdl.vh

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