Skip to content

Add more SystemRDL examples and resulting SystemVerilog #6

@Silicon1602

Description

@Silicon1602

The examples directory is meant to show off certain SystemRDL constructs and what SystemVerilog will be created

  • Counters
  • Hierarchical Interrupts
  • Enums
  • Aliases (including external registers)
  • Interrupts (elaborate example from spec)
  • Parameters

Metadata

Metadata

Assignees

Labels

documentationImprovements or additions to documentation

Projects

No projects

Milestone

No milestone

Relationships

None yet

Development

No branches or pull requests

Issue actions