Fix uart clock initialization

Sh3Rm4n · Sh3Rm4n · commit 15b049b788e4 · 2021-06-18T21:38:46.000+02:00
The clear_bit in at the end of the clock enable was
deleted accidentally. This commit re-adds this call.
diff --git a/src/serial.rs b/src/serial.rs
@@ -514,6 +514,7 @@ macro_rules! usart {
                 fn enable_clock(apb: &mut Self::APB) {
                     apb.enr().modify(|_, w| w.$usartXen().enabled());
                     apb.rstr().modify(|_, w| w.$usartXrst().reset());
+                    apb.rstr().modify(|_, w| w.$usartXrst().clear_bit());
                 }
 
                 fn clock(clocks: &Clocks) -> Hertz {

Original file line number	Diff line number	Diff line change
`@@ -514,6 +514,7 @@ macro_rules! usart {`
`514`	`514`	`fn enable_clock(apb: &mut Self::APB) {`
`515`	`515`	`apb.enr().modify(\|_, w\| w.$usartXen().enabled());`
`516`	`516`	`apb.rstr().modify(\|_, w\| w.$usartXrst().reset());`
	`517`	`+ apb.rstr().modify(\|_, w\| w.$usartXrst().clear_bit());`
`517`	`518`	`}`
`518`	`519`
`519`	`520`	`fn clock(clocks: &Clocks) -> Hertz {`