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| 1 | +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Qualcomm Technologies, Inc. SA87755P Display MDSS |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Mahadevan <quic_mahap@quicinc.com> |
| 11 | + |
| 12 | +description: |
| 13 | + SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like |
| 14 | + DPU display controller, DP interfaces and EDP etc. |
| 15 | + |
| 16 | +$ref: /schemas/display/msm/mdss-common.yaml# |
| 17 | + |
| 18 | +properties: |
| 19 | + compatible: |
| 20 | + const: qcom,sa8775p-mdss |
| 21 | + |
| 22 | + clocks: |
| 23 | + items: |
| 24 | + - description: Display AHB |
| 25 | + - description: Display hf AXI |
| 26 | + - description: Display core |
| 27 | + |
| 28 | + iommus: |
| 29 | + maxItems: 1 |
| 30 | + |
| 31 | + interconnects: |
| 32 | + maxItems: 3 |
| 33 | + |
| 34 | + interconnect-names: |
| 35 | + maxItems: 3 |
| 36 | + |
| 37 | +patternProperties: |
| 38 | + "^display-controller@[0-9a-f]+$": |
| 39 | + type: object |
| 40 | + additionalProperties: true |
| 41 | + |
| 42 | + properties: |
| 43 | + compatible: |
| 44 | + const: qcom,sa8775p-dpu |
| 45 | + |
| 46 | + "^displayport-controller@[0-9a-f]+$": |
| 47 | + type: object |
| 48 | + additionalProperties: true |
| 49 | + |
| 50 | + properties: |
| 51 | + compatible: |
| 52 | + items: |
| 53 | + - const: qcom,sa8775p-dp |
| 54 | + |
| 55 | +required: |
| 56 | + - compatible |
| 57 | + |
| 58 | +unevaluatedProperties: false |
| 59 | + |
| 60 | +examples: |
| 61 | + - | |
| 62 | + #include <dt-bindings/interconnect/qcom,icc.h> |
| 63 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 64 | + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> |
| 65 | + #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> |
| 66 | + #include <dt-bindings/power/qcom,rpmhpd.h> |
| 67 | + #include <dt-bindings/power/qcom-rpmpd.h> |
| 68 | +
|
| 69 | + display-subsystem@ae00000 { |
| 70 | + compatible = "qcom,sa8775p-mdss"; |
| 71 | + reg = <0x0ae00000 0x1000>; |
| 72 | + reg-names = "mdss"; |
| 73 | +
|
| 74 | + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, |
| 75 | + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, |
| 76 | + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; |
| 77 | + interconnect-names = "mdp0-mem", |
| 78 | + "mdp1-mem", |
| 79 | + "cpu-cfg"; |
| 80 | +
|
| 81 | +
|
| 82 | + resets = <&dispcc_core_bcr>; |
| 83 | + power-domains = <&dispcc_gdsc>; |
| 84 | +
|
| 85 | + clocks = <&dispcc_ahb_clk>, |
| 86 | + <&gcc GCC_DISP_HF_AXI_CLK>, |
| 87 | + <&dispcc_mdp_clk>; |
| 88 | +
|
| 89 | + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 90 | + interrupt-controller; |
| 91 | + #interrupt-cells = <1>; |
| 92 | +
|
| 93 | + iommus = <&apps_smmu 0x1000 0x402>; |
| 94 | +
|
| 95 | + #address-cells = <1>; |
| 96 | + #size-cells = <1>; |
| 97 | + ranges; |
| 98 | +
|
| 99 | + display-controller@ae01000 { |
| 100 | + compatible = "qcom,sa8775p-dpu"; |
| 101 | + reg = <0x0ae01000 0x8f000>, |
| 102 | + <0x0aeb0000 0x2008>; |
| 103 | + reg-names = "mdp", "vbif"; |
| 104 | +
|
| 105 | + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, |
| 106 | + <&dispcc_ahb_clk>, |
| 107 | + <&dispcc_mdp_lut_clk>, |
| 108 | + <&dispcc_mdp_clk>, |
| 109 | + <&dispcc_mdp_vsync_clk>; |
| 110 | + clock-names = "nrt_bus", |
| 111 | + "iface", |
| 112 | + "lut", |
| 113 | + "core", |
| 114 | + "vsync"; |
| 115 | +
|
| 116 | + assigned-clocks = <&dispcc_mdp_vsync_clk>; |
| 117 | + assigned-clock-rates = <19200000>; |
| 118 | +
|
| 119 | + operating-points-v2 = <&mdss0_mdp_opp_table>; |
| 120 | + power-domains = <&rpmhpd RPMHPD_MMCX>; |
| 121 | +
|
| 122 | + interrupt-parent = <&mdss0>; |
| 123 | + interrupts = <0>; |
| 124 | +
|
| 125 | + ports { |
| 126 | + #address-cells = <1>; |
| 127 | + #size-cells = <0>; |
| 128 | +
|
| 129 | + port@0 { |
| 130 | + reg = <0>; |
| 131 | + dpu_intf0_out: endpoint { |
| 132 | + remote-endpoint = <&mdss0_dp0_in>; |
| 133 | + }; |
| 134 | + }; |
| 135 | + }; |
| 136 | +
|
| 137 | + mdss0_mdp_opp_table: opp-table { |
| 138 | + compatible = "operating-points-v2"; |
| 139 | +
|
| 140 | + opp-375000000 { |
| 141 | + opp-hz = /bits/ 64 <375000000>; |
| 142 | + required-opps = <&rpmhpd_opp_svs_l1>; |
| 143 | + }; |
| 144 | +
|
| 145 | + opp-500000000 { |
| 146 | + opp-hz = /bits/ 64 <500000000>; |
| 147 | + required-opps = <&rpmhpd_opp_nom>; |
| 148 | + }; |
| 149 | +
|
| 150 | + opp-575000000 { |
| 151 | + opp-hz = /bits/ 64 <575000000>; |
| 152 | + required-opps = <&rpmhpd_opp_turbo>; |
| 153 | + }; |
| 154 | +
|
| 155 | + opp-650000000 { |
| 156 | + opp-hz = /bits/ 64 <650000000>; |
| 157 | + required-opps = <&rpmhpd_opp_turbo_l1>; |
| 158 | + }; |
| 159 | + }; |
| 160 | + }; |
| 161 | +
|
| 162 | + displayport-controller@af54000 { |
| 163 | + compatible = "qcom,sa8775p-dp"; |
| 164 | +
|
| 165 | + pinctrl-0 = <&dp_hot_plug_det>; |
| 166 | + pinctrl-names = "default"; |
| 167 | +
|
| 168 | + reg = <0xaf54000 0x104>, |
| 169 | + <0xaf54200 0x0c0>, |
| 170 | + <0xaf55000 0x770>, |
| 171 | + <0xaf56000 0x09c>; |
| 172 | +
|
| 173 | + interrupt-parent = <&mdss0>; |
| 174 | + interrupts = <12>; |
| 175 | +
|
| 176 | + clocks = <&dispcc_mdss_ahb_clk>, |
| 177 | + <&dispcc_dptx0_aux_clk>, |
| 178 | + <&dispcc_dptx0_link_clk>, |
| 179 | + <&dispcc_dptx0_link_intf_clk>, |
| 180 | + <&dispcc_dptx0_pixel0_clk>; |
| 181 | + clock-names = "core_iface", |
| 182 | + "core_aux", |
| 183 | + "ctrl_link", |
| 184 | + "ctrl_link_iface", |
| 185 | + "stream_pixel"; |
| 186 | +
|
| 187 | + assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, |
| 188 | + <&dispcc_mdss_dptx0_pixel0_clk_src>; |
| 189 | + assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>; |
| 190 | +
|
| 191 | + phys = <&mdss0_edp_phy>; |
| 192 | + phy-names = "dp"; |
| 193 | +
|
| 194 | + operating-points-v2 = <&dp_opp_table>; |
| 195 | + power-domains = <&rpmhpd SA8775P_MMCX>; |
| 196 | +
|
| 197 | + #sound-dai-cells = <0>; |
| 198 | +
|
| 199 | + ports { |
| 200 | + #address-cells = <1>; |
| 201 | + #size-cells = <0>; |
| 202 | +
|
| 203 | + port@0 { |
| 204 | + reg = <0>; |
| 205 | + mdss0_dp0_in: endpoint { |
| 206 | + remote-endpoint = <&dpu_intf0_out>; |
| 207 | + }; |
| 208 | + }; |
| 209 | +
|
| 210 | + port@1 { |
| 211 | + reg = <1>; |
| 212 | + mdss0_dp_out: endpoint { }; |
| 213 | + }; |
| 214 | + }; |
| 215 | +
|
| 216 | + dp_opp_table: opp-table { |
| 217 | + compatible = "operating-points-v2"; |
| 218 | +
|
| 219 | + opp-160000000 { |
| 220 | + opp-hz = /bits/ 64 <160000000>; |
| 221 | + required-opps = <&rpmhpd_opp_low_svs>; |
| 222 | + }; |
| 223 | +
|
| 224 | + opp-270000000 { |
| 225 | + opp-hz = /bits/ 64 <270000000>; |
| 226 | + required-opps = <&rpmhpd_opp_svs>; |
| 227 | + }; |
| 228 | +
|
| 229 | + opp-540000000 { |
| 230 | + opp-hz = /bits/ 64 <540000000>; |
| 231 | + required-opps = <&rpmhpd_opp_svs_l1>; |
| 232 | + }; |
| 233 | +
|
| 234 | + opp-810000000 { |
| 235 | + opp-hz = /bits/ 64 <810000000>; |
| 236 | + required-opps = <&rpmhpd_opp_nom>; |
| 237 | + }; |
| 238 | + }; |
| 239 | + }; |
| 240 | + }; |
| 241 | +... |
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