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Merge tag 'clk-starfive-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into clk-starfive
Pull StarFive clk driver updates from Conor Dooley: Add support for the System-Top-Group, Image-Signal-Process, Video-Output and PLL clocks on the JH7110 SoC. These drivers come with their associate dt-bindings & the obligatory headers containing defines of clock indices. To maintain backwards compatibility, the PLL driver will fall back to using the fixed factor clocks that were merged for v6.4. The binding has been updated to only permit sourcing the PLL clocks from the PLL's clock controller. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'clk-starfive-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: clk: starfive: Add StarFive JH7110 Video-Output clock driver clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver clk: starfive: Add StarFive JH7110 System-Top-Group clock driver clk: starfive: jh7110-sys: Add PLL clocks source from DTS clk: starfive: Add StarFive JH7110 PLL clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs dt-bindings: soc: starfive: Add StarFive syscon module dt-bindings: clock: Add StarFive JH7110 PLL clock generator
2 parents 06c2afb + dae5448 commit fd8c0b5

17 files changed

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‎Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-ispcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: ISP Top core
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- description: ISP Top Axi
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- description: NOC ISP Bus
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- description: external DVP
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clock-names:
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items:
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- const: isp_top_core
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- const: isp_top_axi
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- const: noc_bus_isp_axi
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- const: dvp_clk
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resets:
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items:
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- description: ISP Top core
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- description: ISP Top Axi
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- description: NOC ISP Bus
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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power-domains:
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maxItems: 1
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description:
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ISP domain power
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- '#clock-cells'
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- '#reset-cells'
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <dt-bindings/power/starfive,jh7110-pmu.h>
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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ispcrg: clock-controller@19810000 {
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compatible = "starfive,jh7110-ispcrg";
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reg = <0x19810000 0x10000>;
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clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
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<&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
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<&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
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<&dvp_clk>;
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clock-names = "isp_top_core", "isp_top_axi",
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"noc_bus_isp_axi", "dvp_clk";
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resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
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<&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
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<&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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power-domains = <&pwrc JH7110_PD_ISP>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 PLL Clock Generator
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description:
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These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
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Each PLL works in integer mode or fraction mode, with configuration
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registers in the sys syscon. So the PLLs node should be a child of
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SYS-SYSCON node.
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The formula for calculating frequency is
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Fvco = Fref * (NI + NF) / M / Q1
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-pll
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clocks:
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maxItems: 1
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description: Main Oscillator (24 MHz)
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller {
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compatible = "starfive,jh7110-pll";
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clocks = <&osc>;
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#clock-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 System-Top-Group Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-stgcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Main Oscillator (24 MHz)
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- description: HIFI4 core
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- description: STG AXI/AHB
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- description: USB (125 MHz)
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- description: CPU Bus
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- description: HIFI4 Axi
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- description: NOC STG Bus
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- description: APB Bus
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clock-names:
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items:
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- const: osc
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- const: hifi4_core
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- const: stg_axiahb
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- const: usb_125m
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- const: cpu_bus
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- const: hifi4_axi
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- const: nocstg_bus
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- const: apb_bus
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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stgcrg: clock-controller@10230000 {
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compatible = "starfive,jh7110-stgcrg";
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reg = <0x10230000 0x10000>;
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clocks = <&osc>,
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<&syscrg JH7110_SYSCLK_HIFI4_CORE>,
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<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
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<&syscrg JH7110_SYSCLK_USB_125M>,
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<&syscrg JH7110_SYSCLK_CPU_BUS>,
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<&syscrg JH7110_SYSCLK_HIFI4_AXI>,
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<&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
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<&syscrg JH7110_SYSCLK_APB_BUS>;
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clock-names = "osc", "hifi4_core",
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"stg_axiahb", "usb_125m",
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"cpu_bus", "hifi4_axi",
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"nocstg_bus", "apb_bus";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- description: PLL0
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- description: PLL1
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- description: PLL2
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- items:
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- description: Main Oscillator (24 MHz)
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- description: PLL0
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- description: PLL1
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- description: PLL2
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clock-names:
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oneOf:
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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- const: pll0_out
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- const: pll1_out
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- const: pll2_out
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- items:
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- const: osc
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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- const: pll0_out
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- const: pll1_out
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- const: pll2_out
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'#clock-cells':
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const: 1
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<&gmac1_rgmii_rxin>,
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<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
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<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
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<&tdm_ext>, <&mclk_ext>;
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<&tdm_ext>, <&mclk_ext>,
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<&pllclk 0>, <&pllclk 1>, <&pllclk 2>;
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clock-names = "osc", "gmac1_rmii_refin",
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"gmac1_rgmii_rxin",
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"i2stx_bclk_ext", "i2stx_lrck_ext",
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"i2srx_bclk_ext", "i2srx_lrck_ext",
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"tdm_ext", "mclk_ext";
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"tdm_ext", "mclk_ext",
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"pll0_out", "pll1_out", "pll2_out";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Video-Output Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-voutcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Vout Top core
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- description: Vout Top Ahb
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- description: Vout Top Axi
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- description: Vout Top HDMI MCLK
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- description: I2STX0 BCLK
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- description: external HDMI pixel
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clock-names:
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items:
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- const: vout_src
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- const: vout_top_ahb
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- const: vout_top_axi
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- const: vout_top_hdmitx0_mclk
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- const: i2stx0_bclk
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- const: hdmitx0_pixelclk
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resets:
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maxItems: 1
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description: Vout Top core
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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power-domains:
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maxItems: 1
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description:
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Vout domain power
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- '#clock-cells'
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- '#reset-cells'
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <dt-bindings/power/starfive,jh7110-pmu.h>
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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voutcrg: clock-controller@295C0000 {
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compatible = "starfive,jh7110-voutcrg";
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reg = <0x295C0000 0x10000>;
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clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
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<&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
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<&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
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<&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
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<&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
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<&hdmitx0_pixelclk>;
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clock-names = "vout_src", "vout_top_ahb",
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"vout_top_axi", "vout_top_hdmitx0_mclk",
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"i2stx0_bclk", "hdmitx0_pixelclk";
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resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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power-domains = <&pwrc JH7110_PD_VOUT>;
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};

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