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Kan LiangPeter Zijlstra
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perf/x86/intel: Add a distinct name for Granite Rapids
Currently, the Sapphire Rapids and Granite Rapids share the same PMU name, sapphire_rapids. Because from the kernel’s perspective, GNR is similar to SPR. The only key difference is that they support different extra MSRs. The code path and the PMU name are shared. However, from end users' perspective, they are quite different. Besides the extra MSRs, GNR has a newer PEBS format, supports Retire Latency, supports new CPUID enumeration architecture, doesn't required the load-latency AUX event, has additional TMA Level 1 Architectural Events, etc. The differences can be enumerated by CPUID or the PERF_CAPABILITIES MSR. They weren't reflected in the model-specific kernel setup. But it is worth to have a distinct PMU name for GNR. Fixes: a6742cb ("perf/x86/intel: Fix the FRONTEND encoding on GNR and MTL") Suggested-by: Ahmad Yasin <ahmad.yasin@intel.com> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20240708193336.1192217-3-kan.liang@linux.intel.com
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arch/x86/events/intel/core.c

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6943,12 +6943,18 @@ __init int intel_pmu_init(void)
69436943
case INTEL_EMERALDRAPIDS_X:
69446944
x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
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x86_pmu.extra_regs = intel_glc_extra_regs;
6946-
fallthrough;
6946+
pr_cont("Sapphire Rapids events, ");
6947+
name = "sapphire_rapids";
6948+
goto glc_common;
6949+
69476950
case INTEL_GRANITERAPIDS_X:
69486951
case INTEL_GRANITERAPIDS_D:
6952+
x86_pmu.extra_regs = intel_rwc_extra_regs;
6953+
pr_cont("Granite Rapids events, ");
6954+
name = "granite_rapids";
6955+
6956+
glc_common:
69496957
intel_pmu_init_glc(NULL);
6950-
if (!x86_pmu.extra_regs)
6951-
x86_pmu.extra_regs = intel_rwc_extra_regs;
69526958
x86_pmu.pebs_ept = 1;
69536959
x86_pmu.hw_config = hsw_hw_config;
69546960
x86_pmu.get_event_constraints = glc_get_event_constraints;
@@ -6959,8 +6965,6 @@ __init int intel_pmu_init(void)
69596965
td_attr = glc_td_events_attrs;
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tsx_attr = glc_tsx_events_attrs;
69616967
intel_pmu_pebs_data_source_skl(true);
6962-
pr_cont("Sapphire Rapids events, ");
6963-
name = "sapphire_rapids";
69646968
break;
69656969

69666970
case INTEL_ALDERLAKE:

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