Skip to content

Commit f7b0dff

Browse files
aford173geertu
authored andcommitted
clk: renesas: r8a774a1: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230617150302.38477-2-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent 1bc6f6d commit f7b0dff

File tree

1 file changed

+2
-0
lines changed

1 file changed

+2
-0
lines changed

drivers/clk/renesas/r8a774a1-cpg-mssr.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
7676
/* Core Clock Outputs */
7777
DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
7878
DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
79+
DEF_GEN3_Z("zg", R8A774A1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
7980
DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
8081
DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
8182
DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -123,6 +124,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
123124
};
124125

125126
static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
127+
DEF_MOD("3dge", 112, R8A774A1_CLK_ZG),
126128
DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6),
127129
DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2),
128130
DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2),

0 commit comments

Comments
 (0)