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LoongArch: Re-tab the assembly files
Reflow the *.S files for better stylistic consistency, namely hard tabs after mnemonic position, and vertical alignment of the first operand with hard tabs. Tab width is obviously 8. Some pre-existing intra-block vertical alignments are preserved. Signed-off-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
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+163
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lines changed

7 files changed

+163
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‎arch/loongarch/kernel/entry.S

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ SYM_FUNC_START(handle_syscall)
2727

2828
addi.d sp, sp, -PT_SIZE
2929
cfi_st t2, PT_R3
30-
cfi_rel_offset sp, PT_R3
30+
cfi_rel_offset sp, PT_R3
3131
st.d zero, sp, PT_R0
3232
csrrd t2, LOONGARCH_CSR_PRMD
3333
st.d t2, sp, PT_PRMD
@@ -50,7 +50,7 @@ SYM_FUNC_START(handle_syscall)
5050
cfi_st a7, PT_R11
5151
csrrd ra, LOONGARCH_CSR_ERA
5252
st.d ra, sp, PT_ERA
53-
cfi_rel_offset ra, PT_ERA
53+
cfi_rel_offset ra, PT_ERA
5454

5555
cfi_st tp, PT_R2
5656
cfi_st u0, PT_R21

‎arch/loongarch/kernel/fpu.S

Lines changed: 85 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -27,78 +27,78 @@
2727
.endm
2828

2929
.macro sc_save_fp base
30-
EX fst.d $f0, \base, (0 * FPU_REG_WIDTH)
31-
EX fst.d $f1, \base, (1 * FPU_REG_WIDTH)
32-
EX fst.d $f2, \base, (2 * FPU_REG_WIDTH)
33-
EX fst.d $f3, \base, (3 * FPU_REG_WIDTH)
34-
EX fst.d $f4, \base, (4 * FPU_REG_WIDTH)
35-
EX fst.d $f5, \base, (5 * FPU_REG_WIDTH)
36-
EX fst.d $f6, \base, (6 * FPU_REG_WIDTH)
37-
EX fst.d $f7, \base, (7 * FPU_REG_WIDTH)
38-
EX fst.d $f8, \base, (8 * FPU_REG_WIDTH)
39-
EX fst.d $f9, \base, (9 * FPU_REG_WIDTH)
40-
EX fst.d $f10, \base, (10 * FPU_REG_WIDTH)
41-
EX fst.d $f11, \base, (11 * FPU_REG_WIDTH)
42-
EX fst.d $f12, \base, (12 * FPU_REG_WIDTH)
43-
EX fst.d $f13, \base, (13 * FPU_REG_WIDTH)
44-
EX fst.d $f14, \base, (14 * FPU_REG_WIDTH)
45-
EX fst.d $f15, \base, (15 * FPU_REG_WIDTH)
46-
EX fst.d $f16, \base, (16 * FPU_REG_WIDTH)
47-
EX fst.d $f17, \base, (17 * FPU_REG_WIDTH)
48-
EX fst.d $f18, \base, (18 * FPU_REG_WIDTH)
49-
EX fst.d $f19, \base, (19 * FPU_REG_WIDTH)
50-
EX fst.d $f20, \base, (20 * FPU_REG_WIDTH)
51-
EX fst.d $f21, \base, (21 * FPU_REG_WIDTH)
52-
EX fst.d $f22, \base, (22 * FPU_REG_WIDTH)
53-
EX fst.d $f23, \base, (23 * FPU_REG_WIDTH)
54-
EX fst.d $f24, \base, (24 * FPU_REG_WIDTH)
55-
EX fst.d $f25, \base, (25 * FPU_REG_WIDTH)
56-
EX fst.d $f26, \base, (26 * FPU_REG_WIDTH)
57-
EX fst.d $f27, \base, (27 * FPU_REG_WIDTH)
58-
EX fst.d $f28, \base, (28 * FPU_REG_WIDTH)
59-
EX fst.d $f29, \base, (29 * FPU_REG_WIDTH)
60-
EX fst.d $f30, \base, (30 * FPU_REG_WIDTH)
61-
EX fst.d $f31, \base, (31 * FPU_REG_WIDTH)
30+
EX fst.d $f0, \base, (0 * FPU_REG_WIDTH)
31+
EX fst.d $f1, \base, (1 * FPU_REG_WIDTH)
32+
EX fst.d $f2, \base, (2 * FPU_REG_WIDTH)
33+
EX fst.d $f3, \base, (3 * FPU_REG_WIDTH)
34+
EX fst.d $f4, \base, (4 * FPU_REG_WIDTH)
35+
EX fst.d $f5, \base, (5 * FPU_REG_WIDTH)
36+
EX fst.d $f6, \base, (6 * FPU_REG_WIDTH)
37+
EX fst.d $f7, \base, (7 * FPU_REG_WIDTH)
38+
EX fst.d $f8, \base, (8 * FPU_REG_WIDTH)
39+
EX fst.d $f9, \base, (9 * FPU_REG_WIDTH)
40+
EX fst.d $f10, \base, (10 * FPU_REG_WIDTH)
41+
EX fst.d $f11, \base, (11 * FPU_REG_WIDTH)
42+
EX fst.d $f12, \base, (12 * FPU_REG_WIDTH)
43+
EX fst.d $f13, \base, (13 * FPU_REG_WIDTH)
44+
EX fst.d $f14, \base, (14 * FPU_REG_WIDTH)
45+
EX fst.d $f15, \base, (15 * FPU_REG_WIDTH)
46+
EX fst.d $f16, \base, (16 * FPU_REG_WIDTH)
47+
EX fst.d $f17, \base, (17 * FPU_REG_WIDTH)
48+
EX fst.d $f18, \base, (18 * FPU_REG_WIDTH)
49+
EX fst.d $f19, \base, (19 * FPU_REG_WIDTH)
50+
EX fst.d $f20, \base, (20 * FPU_REG_WIDTH)
51+
EX fst.d $f21, \base, (21 * FPU_REG_WIDTH)
52+
EX fst.d $f22, \base, (22 * FPU_REG_WIDTH)
53+
EX fst.d $f23, \base, (23 * FPU_REG_WIDTH)
54+
EX fst.d $f24, \base, (24 * FPU_REG_WIDTH)
55+
EX fst.d $f25, \base, (25 * FPU_REG_WIDTH)
56+
EX fst.d $f26, \base, (26 * FPU_REG_WIDTH)
57+
EX fst.d $f27, \base, (27 * FPU_REG_WIDTH)
58+
EX fst.d $f28, \base, (28 * FPU_REG_WIDTH)
59+
EX fst.d $f29, \base, (29 * FPU_REG_WIDTH)
60+
EX fst.d $f30, \base, (30 * FPU_REG_WIDTH)
61+
EX fst.d $f31, \base, (31 * FPU_REG_WIDTH)
6262
.endm
6363

6464
.macro sc_restore_fp base
65-
EX fld.d $f0, \base, (0 * FPU_REG_WIDTH)
66-
EX fld.d $f1, \base, (1 * FPU_REG_WIDTH)
67-
EX fld.d $f2, \base, (2 * FPU_REG_WIDTH)
68-
EX fld.d $f3, \base, (3 * FPU_REG_WIDTH)
69-
EX fld.d $f4, \base, (4 * FPU_REG_WIDTH)
70-
EX fld.d $f5, \base, (5 * FPU_REG_WIDTH)
71-
EX fld.d $f6, \base, (6 * FPU_REG_WIDTH)
72-
EX fld.d $f7, \base, (7 * FPU_REG_WIDTH)
73-
EX fld.d $f8, \base, (8 * FPU_REG_WIDTH)
74-
EX fld.d $f9, \base, (9 * FPU_REG_WIDTH)
75-
EX fld.d $f10, \base, (10 * FPU_REG_WIDTH)
76-
EX fld.d $f11, \base, (11 * FPU_REG_WIDTH)
77-
EX fld.d $f12, \base, (12 * FPU_REG_WIDTH)
78-
EX fld.d $f13, \base, (13 * FPU_REG_WIDTH)
79-
EX fld.d $f14, \base, (14 * FPU_REG_WIDTH)
80-
EX fld.d $f15, \base, (15 * FPU_REG_WIDTH)
81-
EX fld.d $f16, \base, (16 * FPU_REG_WIDTH)
82-
EX fld.d $f17, \base, (17 * FPU_REG_WIDTH)
83-
EX fld.d $f18, \base, (18 * FPU_REG_WIDTH)
84-
EX fld.d $f19, \base, (19 * FPU_REG_WIDTH)
85-
EX fld.d $f20, \base, (20 * FPU_REG_WIDTH)
86-
EX fld.d $f21, \base, (21 * FPU_REG_WIDTH)
87-
EX fld.d $f22, \base, (22 * FPU_REG_WIDTH)
88-
EX fld.d $f23, \base, (23 * FPU_REG_WIDTH)
89-
EX fld.d $f24, \base, (24 * FPU_REG_WIDTH)
90-
EX fld.d $f25, \base, (25 * FPU_REG_WIDTH)
91-
EX fld.d $f26, \base, (26 * FPU_REG_WIDTH)
92-
EX fld.d $f27, \base, (27 * FPU_REG_WIDTH)
93-
EX fld.d $f28, \base, (28 * FPU_REG_WIDTH)
94-
EX fld.d $f29, \base, (29 * FPU_REG_WIDTH)
95-
EX fld.d $f30, \base, (30 * FPU_REG_WIDTH)
96-
EX fld.d $f31, \base, (31 * FPU_REG_WIDTH)
65+
EX fld.d $f0, \base, (0 * FPU_REG_WIDTH)
66+
EX fld.d $f1, \base, (1 * FPU_REG_WIDTH)
67+
EX fld.d $f2, \base, (2 * FPU_REG_WIDTH)
68+
EX fld.d $f3, \base, (3 * FPU_REG_WIDTH)
69+
EX fld.d $f4, \base, (4 * FPU_REG_WIDTH)
70+
EX fld.d $f5, \base, (5 * FPU_REG_WIDTH)
71+
EX fld.d $f6, \base, (6 * FPU_REG_WIDTH)
72+
EX fld.d $f7, \base, (7 * FPU_REG_WIDTH)
73+
EX fld.d $f8, \base, (8 * FPU_REG_WIDTH)
74+
EX fld.d $f9, \base, (9 * FPU_REG_WIDTH)
75+
EX fld.d $f10, \base, (10 * FPU_REG_WIDTH)
76+
EX fld.d $f11, \base, (11 * FPU_REG_WIDTH)
77+
EX fld.d $f12, \base, (12 * FPU_REG_WIDTH)
78+
EX fld.d $f13, \base, (13 * FPU_REG_WIDTH)
79+
EX fld.d $f14, \base, (14 * FPU_REG_WIDTH)
80+
EX fld.d $f15, \base, (15 * FPU_REG_WIDTH)
81+
EX fld.d $f16, \base, (16 * FPU_REG_WIDTH)
82+
EX fld.d $f17, \base, (17 * FPU_REG_WIDTH)
83+
EX fld.d $f18, \base, (18 * FPU_REG_WIDTH)
84+
EX fld.d $f19, \base, (19 * FPU_REG_WIDTH)
85+
EX fld.d $f20, \base, (20 * FPU_REG_WIDTH)
86+
EX fld.d $f21, \base, (21 * FPU_REG_WIDTH)
87+
EX fld.d $f22, \base, (22 * FPU_REG_WIDTH)
88+
EX fld.d $f23, \base, (23 * FPU_REG_WIDTH)
89+
EX fld.d $f24, \base, (24 * FPU_REG_WIDTH)
90+
EX fld.d $f25, \base, (25 * FPU_REG_WIDTH)
91+
EX fld.d $f26, \base, (26 * FPU_REG_WIDTH)
92+
EX fld.d $f27, \base, (27 * FPU_REG_WIDTH)
93+
EX fld.d $f28, \base, (28 * FPU_REG_WIDTH)
94+
EX fld.d $f29, \base, (29 * FPU_REG_WIDTH)
95+
EX fld.d $f30, \base, (30 * FPU_REG_WIDTH)
96+
EX fld.d $f31, \base, (31 * FPU_REG_WIDTH)
9797
.endm
9898

9999
.macro sc_save_fcc base, tmp0, tmp1
100100
movcf2gr \tmp0, $fcc0
101-
move \tmp1, \tmp0
101+
move \tmp1, \tmp0
102102
movcf2gr \tmp0, $fcc1
103103
bstrins.d \tmp1, \tmp0, 15, 8
104104
movcf2gr \tmp0, $fcc2
@@ -113,11 +113,11 @@
113113
bstrins.d \tmp1, \tmp0, 55, 48
114114
movcf2gr \tmp0, $fcc7
115115
bstrins.d \tmp1, \tmp0, 63, 56
116-
EX st.d \tmp1, \base, 0
116+
EX st.d \tmp1, \base, 0
117117
.endm
118118

119119
.macro sc_restore_fcc base, tmp0, tmp1
120-
EX ld.d \tmp0, \base, 0
120+
EX ld.d \tmp0, \base, 0
121121
bstrpick.d \tmp1, \tmp0, 7, 0
122122
movgr2cf $fcc0, \tmp1
123123
bstrpick.d \tmp1, \tmp0, 15, 8
@@ -138,11 +138,11 @@
138138

139139
.macro sc_save_fcsr base, tmp0
140140
movfcsr2gr \tmp0, fcsr0
141-
EX st.w \tmp0, \base, 0
141+
EX st.w \tmp0, \base, 0
142142
.endm
143143

144144
.macro sc_restore_fcsr base, tmp0
145-
EX ld.w \tmp0, \base, 0
145+
EX ld.w \tmp0, \base, 0
146146
movgr2fcsr fcsr0, \tmp0
147147
.endm
148148

@@ -151,20 +151,20 @@
151151
*/
152152
SYM_FUNC_START(_save_fp)
153153
fpu_save_csr a0 t1
154-
fpu_save_double a0 t1 # clobbers t1
154+
fpu_save_double a0 t1 # clobbers t1
155155
fpu_save_cc a0 t1 t2 # clobbers t1, t2
156-
jr ra
156+
jr ra
157157
SYM_FUNC_END(_save_fp)
158158
EXPORT_SYMBOL(_save_fp)
159159

160160
/*
161161
* Restore a thread's fp context.
162162
*/
163163
SYM_FUNC_START(_restore_fp)
164-
fpu_restore_double a0 t1 # clobbers t1
165-
fpu_restore_csr a0 t1
166-
fpu_restore_cc a0 t1 t2 # clobbers t1, t2
167-
jr ra
164+
fpu_restore_double a0 t1 # clobbers t1
165+
fpu_restore_csr a0 t1
166+
fpu_restore_cc a0 t1 t2 # clobbers t1, t2
167+
jr ra
168168
SYM_FUNC_END(_restore_fp)
169169

170170
/*
@@ -225,11 +225,11 @@ SYM_FUNC_END(_init_fpu)
225225
* a2: fcsr
226226
*/
227227
SYM_FUNC_START(_save_fp_context)
228-
sc_save_fcc a1 t1 t2
229-
sc_save_fcsr a2 t1
230-
sc_save_fp a0
231-
li.w a0, 0 # success
232-
jr ra
228+
sc_save_fcc a1 t1 t2
229+
sc_save_fcsr a2 t1
230+
sc_save_fp a0
231+
li.w a0, 0 # success
232+
jr ra
233233
SYM_FUNC_END(_save_fp_context)
234234

235235
/*
@@ -238,11 +238,11 @@ SYM_FUNC_END(_save_fp_context)
238238
* a2: fcsr
239239
*/
240240
SYM_FUNC_START(_restore_fp_context)
241-
sc_restore_fp a0
242-
sc_restore_fcc a1 t1 t2
243-
sc_restore_fcsr a2 t1
244-
li.w a0, 0 # success
245-
jr ra
241+
sc_restore_fp a0
242+
sc_restore_fcc a1 t1 t2
243+
sc_restore_fcsr a2 t1
244+
li.w a0, 0 # success
245+
jr ra
246246
SYM_FUNC_END(_restore_fp_context)
247247

248248
SYM_FUNC_START(fault)

‎arch/loongarch/kernel/genex.S

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -35,16 +35,16 @@ SYM_FUNC_START(handle_vint)
3535
BACKUP_T0T1
3636
SAVE_ALL
3737
la.abs t1, __arch_cpu_idle
38-
LONG_L t0, sp, PT_ERA
38+
LONG_L t0, sp, PT_ERA
3939
/* 32 byte rollback region */
4040
ori t0, t0, 0x1f
4141
xori t0, t0, 0x1f
4242
bne t0, t1, 1f
43-
LONG_S t0, sp, PT_ERA
43+
LONG_S t0, sp, PT_ERA
4444
1: move a0, sp
4545
move a1, sp
4646
la.abs t0, do_vint
47-
jirl ra, t0, 0
47+
jirl ra, t0, 0
4848
RESTORE_ALL_AND_RET
4949
SYM_FUNC_END(handle_vint)
5050

@@ -72,7 +72,7 @@ SYM_FUNC_END(except_vec_cex)
7272
build_prep_\prep
7373
move a0, sp
7474
la.abs t0, do_\handler
75-
jirl ra, t0, 0
75+
jirl ra, t0, 0
7676
RESTORE_ALL_AND_RET
7777
SYM_FUNC_END(handle_\exception)
7878
.endm

‎arch/loongarch/kernel/head.S

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -85,8 +85,8 @@ SYM_CODE_START(smpboot_entry)
8585
ld.d sp, t0, CPU_BOOT_STACK
8686
ld.d tp, t0, CPU_BOOT_TINFO
8787

88-
la.abs t0, 0f
89-
jr t0
88+
la.abs t0, 0f
89+
jr t0
9090
0:
9191
bl start_secondary
9292
SYM_CODE_END(smpboot_entry)

‎arch/loongarch/kernel/switch.S

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,8 @@ SYM_FUNC_START(__switch_to)
2424
move tp, a2
2525
cpu_restore_nonscratch a1
2626

27-
li.w t0, _THREAD_SIZE - 32
28-
PTR_ADD t0, t0, tp
27+
li.w t0, _THREAD_SIZE - 32
28+
PTR_ADD t0, t0, tp
2929
set_saved_sp t0, t1, t2
3030

3131
ldptr.d t1, a1, THREAD_CSRPRMD

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