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Merge tag 'irqchip-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier: - Add support for the STM32MP13 variant - Move parent device away from struct irq_chip - Remove all instances of non-const strings assigned to struct irq_chip::name, enabling a nice cleanup for VIC and GIC) - Simplify the Qualcomm PDC driver - A bunch of SiFive PLIC cleanups - Add support for a new variant of the Meson GPIO block - Add support for the irqchip side of the Apple M1 PMU - Add support for the Apple M1 Pro/Max AICv2 irqchip - Add support for the Qualcomm MPM wakeup gadget - Move the Xilinx driver over to the generic irqdomain handling - Tiny speedup for IPIs on GICv3 systems - The usual odd cleanups Link: https://lore.kernel.org/all/20220313105142.704579-1-maz@kernel.org
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‎Documentation/devicetree/bindings/arm/pmu.yaml

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@@ -20,6 +20,8 @@ properties:
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items:
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- enum:
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- apm,potenza-pmu
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- apple,firestorm-pmu
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- apple,icestorm-pmu
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- arm,armv8-pmuv3 # Only for s/w models
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- arm,arm1136-pmu
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- arm,arm1176-pmu

‎Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

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"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
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"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
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"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
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"amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
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- reg : Specifies base physical address and size of the registers.
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- interrupt-controller : Identifies the node as an interrupt controller.
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- #interrupt-cells : Specifies the number of cells needed to encode an

‎Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml

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@@ -56,6 +56,8 @@ properties:
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- 1: virtual HV timer
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- 2: physical guest timer
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- 3: virtual guest timer
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- 4: 'efficient' CPU PMU
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- 5: 'performance' CPU PMU
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The 3rd cell contains the interrupt flags. This is normally
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IRQ_TYPE_LEVEL_HIGH (4).
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power-domains:
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maxItems: 1
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affinities:
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type: object
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additionalProperties: false
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description:
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FIQ affinity can be expressed as a single "affinities" node,
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containing a set of sub-nodes, one per FIQ with a non-default
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affinity.
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patternProperties:
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"^.+-affinity$":
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type: object
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additionalProperties: false
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properties:
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apple,fiq-index:
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description:
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The interrupt number specified as a FIQ, and for which
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the affinity is not the default.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 5
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cpus:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Should be a list of phandles to CPU nodes (as described in
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Documentation/devicetree/bindings/arm/cpus.yaml).
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required:
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- fiq-index
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- cpus
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required:
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- compatible
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- '#interrupt-cells'

‎Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Apple Interrupt Controller 2
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maintainers:
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- Hector Martin <marcan@marcan.st>
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description: |
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The Apple Interrupt Controller 2 is a simple interrupt controller present on
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Apple ARM SoC platforms starting with t600x (M1 Pro and Max).
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It provides the following features:
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- Level-triggered hardware IRQs wired to SoC blocks
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- Single mask bit per IRQ
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- Automatic masking on event delivery (auto-ack)
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- Software triggering (ORed with hw line)
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- Automatic prioritization (single event/ack register per CPU, lower IRQs =
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higher priority)
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- Automatic masking on ack
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- Support for multiple dies
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This device also represents the FIQ interrupt sources on platforms using AIC,
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which do not go through a discrete interrupt controller. It also handles
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FIQ-based Fast IPIs.
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properties:
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compatible:
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items:
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- const: apple,t6000-aic
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- const: apple,aic2
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interrupt-controller: true
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'#interrupt-cells':
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const: 4
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description: |
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The 1st cell contains the interrupt type:
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- 0: Hardware IRQ
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- 1: FIQ
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The 2nd cell contains the die ID.
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The next cell contains the interrupt number.
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- HW IRQs: interrupt number
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- FIQs:
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- 0: physical HV timer
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- 1: virtual HV timer
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- 2: physical guest timer
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- 3: virtual guest timer
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The last cell contains the interrupt flags. This is normally
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IRQ_TYPE_LEVEL_HIGH (4).
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reg:
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items:
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- description: Address and size of the main AIC2 registers.
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- description: Address and size of the AIC2 Event register.
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reg-names:
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items:
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- const: core
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- const: event
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power-domains:
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maxItems: 1
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required:
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- compatible
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- '#interrupt-cells'
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- interrupt-controller
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- reg
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- reg-names
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additionalProperties: false
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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aic: interrupt-controller@28e100000 {
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compatible = "apple,t6000-aic", "apple,aic2";
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#interrupt-cells = <4>;
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interrupt-controller;
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reg = <0x2 0x8e100000 0x0 0xc000>,
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<0x2 0x8e10c000 0x0 0x4>;
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reg-names = "core", "event";
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};
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};

‎Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcom MPM Interrupt Controller
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maintainers:
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- Shawn Guo <shawn.guo@linaro.org>
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description:
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Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
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MSM Power Manager (MPM) that is in always-on domain. In addition to managing
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resources during sleep, the hardware also has an interrupt controller that
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monitors the interrupts when the system is asleep, wakes up the APSS when
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one of these interrupts occur and replays it to GIC interrupt controller
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after GIC becomes operational.
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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items:
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- const: qcom,mpm
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reg:
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maxItems: 1
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description:
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Specifies the base address and size of vMPM registers in RPM MSG RAM.
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interrupts:
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maxItems: 1
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description:
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Specify the IRQ used by RPM to wakeup APSS.
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mboxes:
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maxItems: 1
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description:
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Specify the mailbox used to notify RPM for writing vMPM registers.
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description:
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The first cell is the MPM pin number for the interrupt, and the second
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is the trigger type.
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qcom,mpm-pin-count:
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description:
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Specify the total MPM pin count that a SoC supports.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,mpm-pin-map:
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description:
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A set of MPM pin numbers and the corresponding GIC SPIs.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: MPM pin number
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- description: GIC SPI number for the MPM pin
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required:
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- compatible
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- reg
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- interrupts
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- mboxes
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- interrupt-controller
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- '#interrupt-cells'
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- qcom,mpm-pin-count
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- qcom,mpm-pin-map
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mpm: interrupt-controller@45f01b8 {
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compatible = "qcom,mpm";
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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reg = <0x45f01b8 0x1000>;
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mboxes = <&apcs_glb 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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qcom,mpm-pin-count = <96>;
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qcom,mpm-pin-map = <2 275>,
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<5 296>,
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<12 422>,
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<24 79>,
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<86 183>,
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<90 260>,
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<91 260>;
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};

‎Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml

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- items:
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- enum:
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- st,stm32mp1-exti
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- st,stm32mp13-exti
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- const: syscon
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"#interrupt-cells":

‎MAINTAINERS

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F: Documentation/devicetree/bindings/arm/apple.yaml
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F: Documentation/devicetree/bindings/arm/apple/*
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F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml
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F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
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F: Documentation/devicetree/bindings/interrupt-controller/apple,*
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F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
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F: Documentation/devicetree/bindings/pci/apple,pcie.yaml
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F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml

‎arch/arm64/boot/dts/apple/t8103.dtsi

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<AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu-e {
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compatible = "apple,icestorm-pmu";
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interrupt-parent = <&aic>;
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interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu-p {
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compatible = "apple,firestorm-pmu";
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interrupt-parent = <&aic>;
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interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
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};
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clkref: clock-ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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interrupt-controller;
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reg = <0x2 0x3b100000 0x0 0x8000>;
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power-domains = <&ps_aic>;
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affinities {
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e-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_E>;
232+
cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
233+
};
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p-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_P>;
237+
cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
238+
};
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};
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};
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pmgr: power-management@23b700000 {

‎arch/arm64/include/asm/apple_m1_pmu.h

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// SPDX-License-Identifier: GPL-2.0
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#ifndef __ASM_APPLE_M1_PMU_h
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#define __ASM_APPLE_M1_PMU_h
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#include <linux/bits.h>
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#include <asm/sysreg.h>
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/* Core PMC control register */
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#define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0)
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#define PMCR0_IMODE GENMASK(10, 8)
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#define PMCR0_IMODE_OFF 0
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#define PMCR0_IMODE_PMI 1
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#define PMCR0_IMODE_AIC 2
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#define PMCR0_IMODE_HALT 3
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#define PMCR0_IMODE_FIQ 4
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#define PMCR0_IACT BIT(11)
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#endif /* __ASM_APPLE_M1_PMU_h */

‎arch/microblaze/Kconfig

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select SET_FS
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select ZONE_DMA
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select TRACE_IRQFLAGS_SUPPORT
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select GENERIC_IRQ_MULTI_HANDLER
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select HANDLE_DOMAIN_IRQ
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# Endianness selection
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choice

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