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Merge tag 'iommu-updates-v6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
Pull iommu updates from Joerg Roedel: "Core changes: - Allow ATS on VF when parent device is identity mapped - Optimize unmap path on ARM io-pagetable implementation - Use of_property_present() ARM-SMMU changes: - SMMUv2: - Devicetree binding updates for Qualcomm MMU-500 implementations - Extend workarounds for broken Qualcomm hypervisor to avoid touching features that are not available (e.g. 16KiB page support, reserved context banks) - SMMUv3: - Support for NVIDIA's custom virtual command queue hardware - Fix Stage-2 stall configuration and extend tests to cover this area - A bunch of driver cleanups, including simplification of the master rbtree code - Minor cleanups and fixes across both drivers Intel VT-d changes: - Retire si_domain and convert to use static identity domain - Batched IOTLB/dev-IOTLB invalidation - Small code refactoring and cleanups AMD-Vi changes: - Cleanup and refactoring of io-pagetable code - Add parameter to limit the used io-pagesizes - Other cleanups and fixes" * tag 'iommu-updates-v6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (77 commits) dt-bindings: arm-smmu: Add compatible for QCS8300 SoC iommu/amd: Test for PAGING domains before freeing a domain iommu/amd: Fix argument order in amd_iommu_dev_flush_pasid_all() iommu/amd: Add kernel parameters to limit V1 page-sizes iommu/arm-smmu-v3: Reorganize struct arm_smmu_ctx_desc_cfg iommu/arm-smmu-v3: Add types for each level of the CD table iommu/arm-smmu-v3: Shrink the cdtab l1_desc array iommu/arm-smmu-v3: Do not use devm for the cd table allocations iommu/arm-smmu-v3: Remove strtab_base/cfg iommu/arm-smmu-v3: Reorganize struct arm_smmu_strtab_cfg iommu/arm-smmu-v3: Add types for each level of the 2 level stream table iommu/arm-smmu-v3: Add arm_smmu_strtab_l1/2_idx() iommu/arm-smmu-qcom: apply num_context_bank fixes for SDM630 / SDM660 iommu/arm-smmu-v3: Use the new rb tree helpers dt-bindings: arm-smmu: document the support on SA8255p iommu/tegra241-cmdqv: Do not allocate vcmdq until dma_set_mask_and_coherent iommu/tegra241-cmdqv: Drop static at local variable iommu/tegra241-cmdqv: Fix ioremap() error handling in probe() iommu/amd: Do not set the D bit on AMD v2 table entries iommu/amd: Correct the reported page sizes from the V1 table ...
2 parents c27ea95 + 97162f6 commit eec91e2

31 files changed

+2259
-1040
lines changed

Documentation/admin-guide/kernel-parameters.txt

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -333,12 +333,17 @@
333333
allowed anymore to lift isolation
334334
requirements as needed. This option
335335
does not override iommu=pt
336-
force_enable - Force enable the IOMMU on platforms known
337-
to be buggy with IOMMU enabled. Use this
338-
option with care.
339-
pgtbl_v1 - Use v1 page table for DMA-API (Default).
340-
pgtbl_v2 - Use v2 page table for DMA-API.
341-
irtcachedis - Disable Interrupt Remapping Table (IRT) caching.
336+
force_enable - Force enable the IOMMU on platforms known
337+
to be buggy with IOMMU enabled. Use this
338+
option with care.
339+
pgtbl_v1 - Use v1 page table for DMA-API (Default).
340+
pgtbl_v2 - Use v2 page table for DMA-API.
341+
irtcachedis - Disable Interrupt Remapping Table (IRT) caching.
342+
nohugepages - Limit page-sizes used for v1 page-tables
343+
to 4 KiB.
344+
v2_pgsizes_only - Limit page-sizes used for v1 page-tables
345+
to 4KiB/2Mib/1GiB.
346+
342347

343348
amd_iommu_dump= [HW,X86-64]
344349
Enable AMD IOMMU driver option to dump the ACPI table

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,9 @@ properties:
3636
items:
3737
- enum:
3838
- qcom,qcm2290-smmu-500
39+
- qcom,qcs8300-smmu-500
3940
- qcom,qdu1000-smmu-500
41+
- qcom,sa8255p-smmu-500
4042
- qcom,sa8775p-smmu-500
4143
- qcom,sc7180-smmu-500
4244
- qcom,sc7280-smmu-500
@@ -84,6 +86,7 @@ properties:
8486
items:
8587
- enum:
8688
- qcom,qcm2290-smmu-500
89+
- qcom,sa8255p-smmu-500
8790
- qcom,sa8775p-smmu-500
8891
- qcom,sc7280-smmu-500
8992
- qcom,sc8180x-smmu-500
@@ -552,7 +555,9 @@ allOf:
552555
- cavium,smmu-v2
553556
- marvell,ap806-smmu-500
554557
- nvidia,smmu-500
558+
- qcom,qcs8300-smmu-500
555559
- qcom,qdu1000-smmu-500
560+
- qcom,sa8255p-smmu-500
556561
- qcom,sc7180-smmu-500
557562
- qcom,sdm670-smmu-500
558563
- qcom,sdm845-smmu-500

MAINTAINERS

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22650,6 +22650,7 @@ M: Thierry Reding <thierry.reding@gmail.com>
2265022650
R: Krishna Reddy <vdumpa@nvidia.com>
2265122651
L: linux-tegra@vger.kernel.org
2265222652
S: Supported
22653+
F: drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
2265322654
F: drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
2265422655
F: drivers/iommu/tegra*
2265522656

drivers/iommu/Kconfig

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -424,6 +424,17 @@ config ARM_SMMU_V3_KUNIT_TEST
424424
Enable this option to unit-test arm-smmu-v3 driver functions.
425425

426426
If unsure, say N.
427+
428+
config TEGRA241_CMDQV
429+
bool "NVIDIA Tegra241 CMDQ-V extension support for ARM SMMUv3"
430+
depends on ACPI
431+
help
432+
Support for NVIDIA CMDQ-Virtualization extension for ARM SMMUv3. The
433+
CMDQ-V extension is similar to v3.3 ECMDQ for multi command queues
434+
support, except with virtualization capabilities.
435+
436+
Say Y here if your system is NVIDIA Tegra241 (Grace) or it has the same
437+
CMDQ-V extension.
427438
endif
428439

429440
config S390_IOMMU

drivers/iommu/amd/amd_iommu.h

Lines changed: 2 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -43,9 +43,10 @@ int amd_iommu_enable_faulting(unsigned int cpu);
4343
extern int amd_iommu_guest_ir;
4444
extern enum io_pgtable_fmt amd_iommu_pgtable;
4545
extern int amd_iommu_gpt_level;
46+
extern unsigned long amd_iommu_pgsize_bitmap;
4647

4748
/* Protection domain ops */
48-
struct protection_domain *protection_domain_alloc(unsigned int type);
49+
struct protection_domain *protection_domain_alloc(unsigned int type, int nid);
4950
void protection_domain_free(struct protection_domain *domain);
5051
struct iommu_domain *amd_iommu_domain_alloc_sva(struct device *dev,
5152
struct mm_struct *mm);
@@ -87,14 +88,10 @@ int amd_iommu_complete_ppr(struct device *dev, u32 pasid, int status, int tag);
8788
void amd_iommu_flush_all_caches(struct amd_iommu *iommu);
8889
void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
8990
void amd_iommu_domain_update(struct protection_domain *domain);
90-
void amd_iommu_dev_update_dte(struct iommu_dev_data *dev_data, bool set);
91-
void amd_iommu_domain_flush_complete(struct protection_domain *domain);
9291
void amd_iommu_domain_flush_pages(struct protection_domain *domain,
9392
u64 address, size_t size);
9493
void amd_iommu_dev_flush_pasid_pages(struct iommu_dev_data *dev_data,
9594
ioasid_t pasid, u64 address, size_t size);
96-
void amd_iommu_dev_flush_pasid_all(struct iommu_dev_data *dev_data,
97-
ioasid_t pasid);
9895

9996
#ifdef CONFIG_IRQ_REMAP
10097
int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
@@ -121,11 +118,6 @@ static inline bool check_feature2(u64 mask)
121118
return (amd_iommu_efr2 & mask);
122119
}
123120

124-
static inline int check_feature_gpt_level(void)
125-
{
126-
return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK);
127-
}
128-
129121
static inline bool amd_iommu_gt_ppr_supported(void)
130122
{
131123
return (check_feature(FEATURE_GT) &&
@@ -143,19 +135,6 @@ static inline void *iommu_phys_to_virt(unsigned long paddr)
143135
return phys_to_virt(__sme_clr(paddr));
144136
}
145137

146-
static inline
147-
void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
148-
{
149-
domain->iop.root = (u64 *)(root & PAGE_MASK);
150-
domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */
151-
}
152-
153-
static inline
154-
void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
155-
{
156-
amd_iommu_domain_set_pt_root(domain, 0);
157-
}
158-
159138
static inline int get_pci_sbdf_id(struct pci_dev *pdev)
160139
{
161140
int seg = pci_domain_nr(pdev->bus);
@@ -185,7 +164,6 @@ static inline struct protection_domain *to_pdomain(struct iommu_domain *dom)
185164
}
186165

187166
bool translation_pre_enabled(struct amd_iommu *iommu);
188-
bool amd_iommu_is_attach_deferred(struct device *dev);
189167
int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line);
190168

191169
#ifdef CONFIG_DMI

drivers/iommu/amd/amd_iommu_types.h

Lines changed: 15 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
#ifndef _ASM_X86_AMD_IOMMU_TYPES_H
99
#define _ASM_X86_AMD_IOMMU_TYPES_H
1010

11+
#include <linux/bitfield.h>
1112
#include <linux/iommu.h>
1213
#include <linux/types.h>
1314
#include <linux/mmu_notifier.h>
@@ -95,26 +96,21 @@
9596
#define FEATURE_GA BIT_ULL(7)
9697
#define FEATURE_HE BIT_ULL(8)
9798
#define FEATURE_PC BIT_ULL(9)
98-
#define FEATURE_GATS_SHIFT (12)
99-
#define FEATURE_GATS_MASK (3ULL)
99+
#define FEATURE_GATS GENMASK_ULL(13, 12)
100+
#define FEATURE_GLX GENMASK_ULL(15, 14)
100101
#define FEATURE_GAM_VAPIC BIT_ULL(21)
102+
#define FEATURE_PASMAX GENMASK_ULL(36, 32)
101103
#define FEATURE_GIOSUP BIT_ULL(48)
102104
#define FEATURE_HASUP BIT_ULL(49)
103105
#define FEATURE_EPHSUP BIT_ULL(50)
104106
#define FEATURE_HDSUP BIT_ULL(52)
105107
#define FEATURE_SNP BIT_ULL(63)
106108

107-
#define FEATURE_PASID_SHIFT 32
108-
#define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
109-
110-
#define FEATURE_GLXVAL_SHIFT 14
111-
#define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
112109

113110
/* Extended Feature 2 Bits */
114-
#define FEATURE_SNPAVICSUP_SHIFT 5
115-
#define FEATURE_SNPAVICSUP_MASK (0x07ULL << FEATURE_SNPAVICSUP_SHIFT)
111+
#define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5)
116112
#define FEATURE_SNPAVICSUP_GAM(x) \
117-
((x & FEATURE_SNPAVICSUP_MASK) >> FEATURE_SNPAVICSUP_SHIFT == 0x1)
113+
(FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
118114

119115
/* Note:
120116
* The current driver only support 16-bit PASID.
@@ -294,8 +290,13 @@
294290
* that we support.
295291
*
296292
* 512GB Pages are not supported due to a hardware bug
293+
* Page sizes >= the 52 bit max physical address of the CPU are not supported.
297294
*/
298-
#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
295+
#define AMD_IOMMU_PGSIZES (GENMASK_ULL(51, 12) ^ SZ_512G)
296+
297+
/* Special mode where page-sizes are limited to 4 KiB */
298+
#define AMD_IOMMU_PGSIZES_4K (PAGE_SIZE)
299+
299300
/* 4K, 2MB, 1G page sizes are supported */
300301
#define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30))
301302

@@ -419,10 +420,6 @@
419420
#define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
420421
#define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0x1fffffULL)
421422

422-
#define DTE_GCR3_INDEX_A 0
423-
#define DTE_GCR3_INDEX_B 1
424-
#define DTE_GCR3_INDEX_C 1
425-
426423
#define DTE_GCR3_SHIFT_A 58
427424
#define DTE_GCR3_SHIFT_B 16
428425
#define DTE_GCR3_SHIFT_C 43
@@ -527,7 +524,7 @@ struct amd_irte_ops;
527524
#define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0)
528525

529526
#define io_pgtable_to_data(x) \
530-
container_of((x), struct amd_io_pgtable, iop)
527+
container_of((x), struct amd_io_pgtable, pgtbl)
531528

532529
#define io_pgtable_ops_to_data(x) \
533530
io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
@@ -537,7 +534,7 @@ struct amd_irte_ops;
537534
struct protection_domain, iop)
538535

539536
#define io_pgtable_cfg_to_data(x) \
540-
container_of((x), struct amd_io_pgtable, pgtbl_cfg)
537+
container_of((x), struct amd_io_pgtable, pgtbl.cfg)
541538

542539
struct gcr3_tbl_info {
543540
u64 *gcr3_tbl; /* Guest CR3 table */
@@ -547,8 +544,7 @@ struct gcr3_tbl_info {
547544
};
548545

549546
struct amd_io_pgtable {
550-
struct io_pgtable_cfg pgtbl_cfg;
551-
struct io_pgtable iop;
547+
struct io_pgtable pgtbl;
552548
int mode;
553549
u64 *root;
554550
u64 *pgd; /* v2 pgtable pgd pointer */
@@ -580,7 +576,6 @@ struct protection_domain {
580576
struct amd_io_pgtable iop;
581577
spinlock_t lock; /* mostly used to lock the page table*/
582578
u16 id; /* the domain id written to the device table */
583-
int nid; /* Node ID */
584579
enum protection_domain_mode pd_mode; /* Track page table type */
585580
bool dirty_tracking; /* dirty tracking is enabled in the domain */
586581
unsigned dev_cnt; /* devices assigned to this domain */

drivers/iommu/amd/init.c

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -192,6 +192,8 @@ bool amdr_ivrs_remap_support __read_mostly;
192192

193193
bool amd_iommu_force_isolation __read_mostly;
194194

195+
unsigned long amd_iommu_pgsize_bitmap __ro_after_init = AMD_IOMMU_PGSIZES;
196+
195197
/*
196198
* AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
197199
* to know which ones are already in use.
@@ -2042,14 +2044,12 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
20422044
int glxval;
20432045
u64 pasmax;
20442046

2045-
pasmax = amd_iommu_efr & FEATURE_PASID_MASK;
2046-
pasmax >>= FEATURE_PASID_SHIFT;
2047+
pasmax = FIELD_GET(FEATURE_PASMAX, amd_iommu_efr);
20472048
iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1;
20482049

20492050
BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK);
20502051

2051-
glxval = amd_iommu_efr & FEATURE_GLXVAL_MASK;
2052-
glxval >>= FEATURE_GLXVAL_SHIFT;
2052+
glxval = FIELD_GET(FEATURE_GLX, amd_iommu_efr);
20532053

20542054
if (amd_iommu_max_glx_val == -1)
20552055
amd_iommu_max_glx_val = glxval;
@@ -3088,7 +3088,7 @@ static int __init early_amd_iommu_init(void)
30883088

30893089
/* 5 level guest page table */
30903090
if (cpu_feature_enabled(X86_FEATURE_LA57) &&
3091-
check_feature_gpt_level() == GUEST_PGTABLE_5_LEVEL)
3091+
FIELD_GET(FEATURE_GATS, amd_iommu_efr) == GUEST_PGTABLE_5_LEVEL)
30923092
amd_iommu_gpt_level = PAGE_MODE_5_LEVEL;
30933093

30943094
/* Disable any previously enabled IOMMUs */
@@ -3494,6 +3494,12 @@ static int __init parse_amd_iommu_options(char *str)
34943494
amd_iommu_pgtable = AMD_IOMMU_V2;
34953495
} else if (strncmp(str, "irtcachedis", 11) == 0) {
34963496
amd_iommu_irtcachedis = true;
3497+
} else if (strncmp(str, "nohugepages", 11) == 0) {
3498+
pr_info("Restricting V1 page-sizes to 4KiB");
3499+
amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_4K;
3500+
} else if (strncmp(str, "v2_pgsizes_only", 15) == 0) {
3501+
pr_info("Restricting V1 page-sizes to 4KiB/2MiB/1GiB");
3502+
amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_V2;
34973503
} else {
34983504
pr_notice("Unknown option - '%s'\n", str);
34993505
}

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