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clk: mediatek: Add MT8188 vppsys0 clock support
Add MT8188 vppsys0 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-16-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/mediatek/Kconfig

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@@ -741,6 +741,13 @@ config COMMON_CLK_MT8188_VENCSYS
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help
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This driver supports MediaTek MT8188 vencsys clocks.
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config COMMON_CLK_MT8188_VPPSYS
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tristate "Clock driver for MediaTek MT8188 vppsys"
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depends on COMMON_CLK_MT8188
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default COMMON_CLK_MT8188
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help
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This driver supports MediaTek MT8188 vppsys0/1 clocks.
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config COMMON_CLK_MT8192
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tristate "Clock driver for MediaTek MT8192"
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depends on ARM64 || COMPILE_TEST

‎drivers/clk/mediatek/Makefile

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@@ -109,6 +109,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_MFGCFG) += clk-mt8188-mfg.o
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obj-$(CONFIG_COMMON_CLK_MT8188_VDECSYS) += clk-mt8188-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) += clk-mt8188-vdo0.o clk-mt8188-vdo1.o
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obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) += clk-mt8188-venc.o
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obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) += clk-mt8188-vpp0.o
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obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
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obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
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obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

‎drivers/clk/mediatek/clk-mt8188-vpp0.c

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Garmin Chang <garmin.chang@mediatek.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8188-clk.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs vpp0_0_cg_regs = {
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.set_ofs = 0x24,
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.clr_ofs = 0x28,
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.sta_ofs = 0x20,
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};
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static const struct mtk_gate_regs vpp0_1_cg_regs = {
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.set_ofs = 0x30,
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.clr_ofs = 0x34,
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.sta_ofs = 0x2c,
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};
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static const struct mtk_gate_regs vpp0_2_cg_regs = {
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.set_ofs = 0x3c,
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.clr_ofs = 0x40,
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.sta_ofs = 0x38,
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};
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#define GATE_VPP0_0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_VPP0_1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_VPP0_2(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate vpp0_clks[] = {
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/* VPP0_0 */
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GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
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GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
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GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7),
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GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8),
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GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
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GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
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GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
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GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay", "top_vpp", 14),
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GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
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GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16),
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GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17),
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GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18),
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/* VPP0_1 */
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GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM, "vpp0_smi_common_mmsram", "top_vpp", 0),
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GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM, "vpp0_gals_vdo0_larb0_mmsram", "top_vpp", 1),
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GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM, "vpp0_gals_vdo0_larb1_mmsram", "top_vpp", 2),
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GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM, "vpp0_gals_vencsys_mmsram", "top_vpp", 3),
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GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM,
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"vpp0_gals_vencsys_core1_mmsram", "top_vpp", 4),
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GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM, "vpp0_gals_infra_mmsram", "top_vpp", 5),
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GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM, "vpp0_gals_camsys_mmsram", "top_vpp", 6),
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GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM, "vpp0_gals_vpp1_larb5_mmsram", "top_vpp", 7),
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GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM, "vpp0_gals_vpp1_larb6_mmsram", "top_vpp", 8),
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GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM, "vpp0_smi_reorder_mmsram", "top_vpp", 9),
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GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10),
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GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11),
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GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12),
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GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13),
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GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16),
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GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17),
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GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18),
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GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19),
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GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
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GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS, "vpp0_gals_vpp1_wpesys", "top_vpp", 21),
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GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1,
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"vpp0_gals_vdo0_vdo1_vencsys_core1", "top_vpp", 22),
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GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23),
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GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24),
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GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25),
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GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26),
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GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27),
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GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, "vpp0_dsip_rdma", "top_vpp", 28),
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GATE_VPP0_1(CLK_VPP0_DISP_WDMA, "vpp0_disp_wdma", "top_vpp", 29),
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GATE_VPP0_1(CLK_VPP0_MDP_HMS, "vpp0_mdp_hms", "top_vpp", 30),
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/* VPP0_2 */
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GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0),
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GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, "vpp0_warp0_async", "top_wpe_vpp", 1),
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GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
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GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, "vpp0_warp1_async", "top_wpe_vpp", 3),
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};
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static const struct mtk_clk_desc vpp0_desc = {
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.clks = vpp0_clks,
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.num_clks = ARRAY_SIZE(vpp0_clks),
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};
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static const struct platform_device_id clk_mt8188_vpp0_id_table[] = {
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{ .name = "clk-mt8188-vpp0", .driver_data = (kernel_ulong_t)&vpp0_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(platform, clk_mt8188_vpp0_id_table);
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static struct platform_driver clk_mt8188_vpp0_drv = {
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.probe = mtk_clk_pdev_probe,
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.remove = mtk_clk_pdev_remove,
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.driver = {
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.name = "clk-mt8188-vpp0",
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},
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.id_table = clk_mt8188_vpp0_id_table,
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};
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module_platform_driver(clk_mt8188_vpp0_drv);
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MODULE_LICENSE("GPL");

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