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clk: qcom: dispcc-sm8450: fix DisplayPort clocks
On SM8450 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. This fixes frequency selection in the OPP core (which otherwise attempts to use invalid 810 KHz as DP link rate), also fixing the following message: msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22 Fixes: 16fb89f ("clk: qcom: Add support for Display Clock Controller on SM8450") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-1-b44038f3fa96@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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drivers/clk/qcom/dispcc-sm8450.c

Lines changed: 4 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -309,26 +309,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
309309
},
310310
};
311311

312-
static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
313-
F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
314-
F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
315-
F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
316-
F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
317-
{ }
318-
};
319-
320312
static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
321313
.cmd_rcgr = 0x819c,
322314
.mnd_width = 0,
323315
.hid_width = 5,
324316
.parent_map = disp_cc_parent_map_3,
325-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
326317
.clkr.hw.init = &(struct clk_init_data) {
327318
.name = "disp_cc_mdss_dptx0_link_clk_src",
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.parent_data = disp_cc_parent_data_3,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
330321
.flags = CLK_SET_RATE_PARENT,
331-
.ops = &clk_rcg2_ops,
322+
.ops = &clk_byte2_ops,
332323
},
333324
};
334325

@@ -382,13 +373,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
382373
.mnd_width = 0,
383374
.hid_width = 5,
384375
.parent_map = disp_cc_parent_map_3,
385-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
386376
.clkr.hw.init = &(struct clk_init_data) {
387377
.name = "disp_cc_mdss_dptx1_link_clk_src",
388378
.parent_data = disp_cc_parent_data_3,
389379
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
390380
.flags = CLK_SET_RATE_PARENT,
391-
.ops = &clk_rcg2_ops,
381+
.ops = &clk_byte2_ops,
392382
},
393383
};
394384

@@ -442,13 +432,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
442432
.mnd_width = 0,
443433
.hid_width = 5,
444434
.parent_map = disp_cc_parent_map_3,
445-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
446435
.clkr.hw.init = &(struct clk_init_data) {
447436
.name = "disp_cc_mdss_dptx2_link_clk_src",
448437
.parent_data = disp_cc_parent_data_3,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
450439
.flags = CLK_SET_RATE_PARENT,
451-
.ops = &clk_rcg2_ops,
440+
.ops = &clk_byte2_ops,
452441
},
453442
};
454443

@@ -502,13 +491,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
502491
.mnd_width = 0,
503492
.hid_width = 5,
504493
.parent_map = disp_cc_parent_map_3,
505-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
506494
.clkr.hw.init = &(struct clk_init_data) {
507495
.name = "disp_cc_mdss_dptx3_link_clk_src",
508496
.parent_data = disp_cc_parent_data_3,
509497
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
510498
.flags = CLK_SET_RATE_PARENT,
511-
.ops = &clk_rcg2_ops,
499+
.ops = &clk_byte2_ops,
512500
},
513501
};
514502

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