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clocksource/drivers/loongson1: Move PWM timer to clocksource framework
This patch moves most part of arch/mips/loongson32/common/time.c into drivers/clocksource. Adapt the driver to clocksource framework with devicetree support and updates Kconfig/Makefile options. Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20230512103724.587760-4-keguang.zhang@gmail.com
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drivers/clocksource/Kconfig

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@@ -612,6 +612,15 @@ config TIMER_IMX_SYS_CTR
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Enable this option to use i.MX system counter timer as a
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clockevent.
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config CLKSRC_LOONGSON1_PWM
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bool "Clocksource using Loongson1 PWM"
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depends on MACH_LOONGSON32 || COMPILE_TEST
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select MIPS_EXTERNAL_TIMER
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select TIMER_OF
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help
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Enable this option to use Loongson1 PWM timer as clocksource
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instead of the performance counter.
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config CLKSRC_ST_LPC
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bool "Low power clocksource found in the LPC" if COMPILE_TEST
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select TIMER_OF if OF

drivers/clocksource/Makefile

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@@ -89,3 +89,4 @@ obj-$(CONFIG_MICROCHIP_PIT64B) += timer-microchip-pit64b.o
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obj-$(CONFIG_MSC313E_TIMER) += timer-msc313e.o
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obj-$(CONFIG_GOLDFISH_TIMER) += timer-goldfish.o
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obj-$(CONFIG_GXP_TIMER) += timer-gxp.o
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obj-$(CONFIG_CLKSRC_LOONGSON1_PWM) += timer-loongson1-pwm.o
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Clocksource driver for Loongson-1 SoC
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*
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* Copyright (c) 2023 Keguang Zhang <keguang.zhang@gmail.com>
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/sizes.h>
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#include "timer-of.h"
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/* Loongson-1 PWM Timer Register Definitions */
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#define PWM_CNTR 0x0
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#define PWM_HRC 0x4
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#define PWM_LRC 0x8
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#define PWM_CTRL 0xc
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/* PWM Control Register Bits */
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#define INT_LRC_EN BIT(11)
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#define INT_HRC_EN BIT(10)
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#define CNTR_RST BIT(7)
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#define INT_SR BIT(6)
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#define INT_EN BIT(5)
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#define PWM_SINGLE BIT(4)
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#define PWM_OE BIT(3)
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#define CNT_EN BIT(0)
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#define CNTR_WIDTH 24
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DEFINE_RAW_SPINLOCK(ls1x_timer_lock);
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struct ls1x_clocksource {
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void __iomem *reg_base;
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unsigned long ticks_per_jiffy;
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struct clocksource clksrc;
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};
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static inline struct ls1x_clocksource *to_ls1x_clksrc(struct clocksource *c)
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{
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return container_of(c, struct ls1x_clocksource, clksrc);
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}
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static inline void ls1x_pwmtimer_set_period(unsigned int period,
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struct timer_of *to)
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{
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writel(period, timer_of_base(to) + PWM_LRC);
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writel(period, timer_of_base(to) + PWM_HRC);
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}
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static inline void ls1x_pwmtimer_clear(struct timer_of *to)
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{
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writel(0, timer_of_base(to) + PWM_CNTR);
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}
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static inline void ls1x_pwmtimer_start(struct timer_of *to)
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{
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writel((INT_EN | PWM_OE | CNT_EN), timer_of_base(to) + PWM_CTRL);
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}
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static inline void ls1x_pwmtimer_stop(struct timer_of *to)
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{
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writel(0, timer_of_base(to) + PWM_CTRL);
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}
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static inline void ls1x_pwmtimer_irq_ack(struct timer_of *to)
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{
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int val;
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val = readl(timer_of_base(to) + PWM_CTRL);
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val |= INT_SR;
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writel(val, timer_of_base(to) + PWM_CTRL);
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}
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static irqreturn_t ls1x_clockevent_isr(int irq, void *dev_id)
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{
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struct clock_event_device *clkevt = dev_id;
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struct timer_of *to = to_timer_of(clkevt);
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ls1x_pwmtimer_irq_ack(to);
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ls1x_pwmtimer_clear(to);
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ls1x_pwmtimer_start(to);
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clkevt->event_handler(clkevt);
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return IRQ_HANDLED;
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}
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static int ls1x_clockevent_set_state_periodic(struct clock_event_device *clkevt)
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{
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struct timer_of *to = to_timer_of(clkevt);
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raw_spin_lock(&ls1x_timer_lock);
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ls1x_pwmtimer_set_period(timer_of_period(to), to);
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ls1x_pwmtimer_clear(to);
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ls1x_pwmtimer_start(to);
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raw_spin_unlock(&ls1x_timer_lock);
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return 0;
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}
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static int ls1x_clockevent_tick_resume(struct clock_event_device *clkevt)
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{
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raw_spin_lock(&ls1x_timer_lock);
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ls1x_pwmtimer_start(to_timer_of(clkevt));
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raw_spin_unlock(&ls1x_timer_lock);
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return 0;
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}
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static int ls1x_clockevent_set_state_shutdown(struct clock_event_device *clkevt)
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{
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raw_spin_lock(&ls1x_timer_lock);
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ls1x_pwmtimer_stop(to_timer_of(clkevt));
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raw_spin_unlock(&ls1x_timer_lock);
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return 0;
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}
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static int ls1x_clockevent_set_next(unsigned long evt,
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struct clock_event_device *clkevt)
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{
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struct timer_of *to = to_timer_of(clkevt);
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raw_spin_lock(&ls1x_timer_lock);
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ls1x_pwmtimer_set_period(evt, to);
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ls1x_pwmtimer_clear(to);
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ls1x_pwmtimer_start(to);
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raw_spin_unlock(&ls1x_timer_lock);
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return 0;
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}
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static struct timer_of ls1x_to = {
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.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
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.clkevt = {
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.name = "ls1x-pwmtimer",
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.rating = 300,
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.set_next_event = ls1x_clockevent_set_next,
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.set_state_periodic = ls1x_clockevent_set_state_periodic,
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.set_state_oneshot = ls1x_clockevent_set_state_shutdown,
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.set_state_shutdown = ls1x_clockevent_set_state_shutdown,
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.tick_resume = ls1x_clockevent_tick_resume,
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},
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.of_irq = {
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.handler = ls1x_clockevent_isr,
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.flags = IRQF_TIMER,
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},
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};
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/*
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* Since the PWM timer overflows every two ticks, its not very useful
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* to just read by itself. So use jiffies to emulate a free
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* running counter:
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*/
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static u64 ls1x_clocksource_read(struct clocksource *cs)
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{
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struct ls1x_clocksource *ls1x_cs = to_ls1x_clksrc(cs);
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unsigned long flags;
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int count;
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u32 jifs;
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static int old_count;
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static u32 old_jifs;
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raw_spin_lock_irqsave(&ls1x_timer_lock, flags);
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/*
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* Although our caller may have the read side of xtime_lock,
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* this is now a seqlock, and we are cheating in this routine
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* by having side effects on state that we cannot undo if
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* there is a collision on the seqlock and our caller has to
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* retry. (Namely, old_jifs and old_count.) So we must treat
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* jiffies as volatile despite the lock. We read jiffies
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* before latching the timer count to guarantee that although
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* the jiffies value might be older than the count (that is,
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* the counter may underflow between the last point where
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* jiffies was incremented and the point where we latch the
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* count), it cannot be newer.
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*/
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jifs = jiffies;
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/* read the count */
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count = readl(ls1x_cs->reg_base + PWM_CNTR);
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/*
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* It's possible for count to appear to go the wrong way for this
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* reason:
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*
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* The timer counter underflows, but we haven't handled the resulting
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* interrupt and incremented jiffies yet.
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*
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* Previous attempts to handle these cases intelligently were buggy, so
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* we just do the simple thing now.
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*/
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if (count < old_count && jifs == old_jifs)
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count = old_count;
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old_count = count;
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old_jifs = jifs;
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raw_spin_unlock_irqrestore(&ls1x_timer_lock, flags);
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return (u64)(jifs * ls1x_cs->ticks_per_jiffy) + count;
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}
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static struct ls1x_clocksource ls1x_clocksource = {
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.clksrc = {
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.name = "ls1x-pwmtimer",
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.rating = 300,
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.read = ls1x_clocksource_read,
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.mask = CLOCKSOURCE_MASK(CNTR_WIDTH),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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},
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};
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static int __init ls1x_pwm_clocksource_init(struct device_node *np)
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{
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struct timer_of *to = &ls1x_to;
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int ret;
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ret = timer_of_init(np, to);
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if (ret)
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return ret;
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clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
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0x1, GENMASK(CNTR_WIDTH - 1, 0));
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ls1x_clocksource.reg_base = timer_of_base(to);
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ls1x_clocksource.ticks_per_jiffy = timer_of_period(to);
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return clocksource_register_hz(&ls1x_clocksource.clksrc,
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timer_of_rate(to));
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}
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TIMER_OF_DECLARE(ls1x_pwm_clocksource, "loongson,ls1b-pwmtimer",
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ls1x_pwm_clocksource_init);

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