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clk: mediatek: Add MT8188 vdosys0 clock support
Add MT8188 vdosys0 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-13-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/mediatek/Kconfig

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@@ -727,6 +727,13 @@ config COMMON_CLK_MT8188_VDECSYS
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help
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This driver supports MediaTek MT8188 vdecsys and vdecsys_soc clocks.
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config COMMON_CLK_MT8188_VDOSYS
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tristate "Clock driver for MediaTek MT8188 vdosys"
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depends on COMMON_CLK_MT8188
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default COMMON_CLK_MT8188
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help
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This driver supports MediaTek MT8188 vdosys0/1 (multimedia) clocks.
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config COMMON_CLK_MT8192
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tristate "Clock driver for MediaTek MT8192"
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depends on ARM64 || COMPILE_TEST

‎drivers/clk/mediatek/Makefile

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@@ -107,6 +107,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_IMGSYS) += clk-mt8188-img.o
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obj-$(CONFIG_COMMON_CLK_MT8188_IPESYS) += clk-mt8188-ipe.o
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obj-$(CONFIG_COMMON_CLK_MT8188_MFGCFG) += clk-mt8188-mfg.o
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obj-$(CONFIG_COMMON_CLK_MT8188_VDECSYS) += clk-mt8188-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) += clk-mt8188-vdo0.o
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obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
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obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
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obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

‎drivers/clk/mediatek/clk-mt8188-vdo0.c

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Garmin Chang <garmin.chang@mediatek.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8188-clk.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs vdo0_0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs vdo0_1_cg_regs = {
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.set_ofs = 0x114,
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.clr_ofs = 0x118,
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.sta_ofs = 0x110,
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};
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static const struct mtk_gate_regs vdo0_2_cg_regs = {
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.set_ofs = 0x124,
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.clr_ofs = 0x128,
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.sta_ofs = 0x120,
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};
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#define GATE_VDO0_0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_VDO0_1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_VDO0_2(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
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GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr, _flags)
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static const struct mtk_gate vdo0_clks[] = {
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/* VDO0_0 */
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GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0),
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GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 2),
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GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4),
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GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 6),
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GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8),
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GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10),
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GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17),
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GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19),
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GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
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GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
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GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23),
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GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24),
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GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25),
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GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 26),
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GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0", "top_vpp", 27),
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GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28),
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GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 29),
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GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0", "top_vpp", 30),
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GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0", "top_vpp", 31),
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/* VDO0_1 */
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GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, "vdo0_disp_postmask0", "top_vpp", 0),
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GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 1),
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GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 5),
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GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3", "top_vpp", 6),
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GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4", "top_vpp", 7),
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GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10),
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GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11),
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GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12),
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GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13),
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GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14),
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GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15),
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/* VDO0_2 */
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GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0),
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GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8),
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GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf",
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"top_edp", 16, CLK_SET_RATE_PARENT),
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};
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static const struct mtk_clk_desc vdo0_desc = {
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.clks = vdo0_clks,
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.num_clks = ARRAY_SIZE(vdo0_clks),
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};
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static const struct platform_device_id clk_mt8188_vdo0_id_table[] = {
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{ .name = "clk-mt8188-vdo0", .driver_data = (kernel_ulong_t)&vdo0_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(platform, clk_mt8188_vdo0_id_table);
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static struct platform_driver clk_mt8188_vdo0_drv = {
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.probe = mtk_clk_pdev_probe,
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.remove = mtk_clk_pdev_remove,
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.driver = {
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.name = "clk-mt8188-vdo0",
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},
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.id_table = clk_mt8188_vdo0_id_table,
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};
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module_platform_driver(clk_mt8188_vdo0_drv);
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MODULE_LICENSE("GPL");

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